A logarithmic detector amplifying (LDA) system is provided for use as a high sensitivity receive booster or replacement for a low noise amplifier in a receive chain of a communication device. The LDA system includes an amplifying circuit configured to receive an input signal having a first frequency and generate an oscillation based on the input signal, a sampling circuit coupled to the amplifying circuit and configured to terminate the oscillation based on a predetermined threshold to periodically clamp and restart the oscillation to generate a series of pulses modulated by the oscillation and by the input signal, and one or more resonant circuits coupled with the amplifying circuit and configured to establish a frequency of operation and to generate an output signal having a second frequency, the second frequency being substantially the same as the first frequency.

The present disclosure relates to a radio frequency (RF) power transistor package. It further relates to a mobile telecommunications base station comprising such an RF power transistor package, and to an integrated passive die suitable for use in an RF power amplifier package. In example embodiments, an in-package impedance network is used that is connected to an output of the RF power transistor arranged inside the package. This network comprises a first inductive element having a first and second terminal, the first terminal being electrically connected to the output of the RF transistor, a resonance unit electrically connected to the second terminal of the first inductive element, and a second capacitive element electrically connected in between the resonance unit and ground, where the first capacitive element is arranged in series with the second capacitive element.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

A radio frequency integrated circuit includes an amplification circuit for outputting a radio frequency signal to an antenna, a balun including a first terminal, a second terminal, a third terminal, and a fourth terminal, and a variable capacitance circuit including a fifth terminal and a sixth terminal. The first terminal and the second terminal of the balun receive output signals of the amplification circuit. The third terminal and the fourth terminal of the balun are connected to the fifth terminal and the sixth terminal of the variable capacitance circuit, respectively, and the fifth terminal is connected to a radio frequency output terminal. The variable capacitance circuit includes a plurality of capacity cells that are connected in parallel between two output terminals.

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source input stage and a common gate output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.

A power amplifying device includes a first amplification circuit amplifying a first signal having a first frequency component and a second frequency component; a second amplification circuit amplifying a second signal received through an output node of the first amplification circuit; a filter circuit connected between a ground node of the first amplification circuit and a common ground to pass the first and second frequency components to the common ground through the ground node; and an inverting circuit that phase-inverts a signal including second harmonic components of the first and second frequency components that are received through the ground node of the first amplification circuit and provide the phase inverted signal to the output node of the first amplification circuit.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

The present disclosure relates to a radio frequency (RF) power transistor package. It further relates to a mobile telecommunications base station comprising such an RF power transistor package, and to an integrated passive die suitable for use in an RF power amplifier package. In example embodiments, an in-package impedance network is used that is connected to an output of the RF power transistor arranged inside the package. This network comprises a first inductive element having a first and second terminal, the first terminal being electrically connected to the output of the RF transistor, a resonance unit electrically connected to the second terminal of the first inductive element, and a second capacitive element electrically connected in between the resonance unit and ground, where the first capacitive element is arranged in series with the second capacitive element.

Provided is a load modulation amplifier including: a high frequency circuit board; and on the board, an input distribution circuit unit (DC) including: a distributor for dividing one input signal into two signals IS1 and IS2; and a phase delay circuit formed on a signal line for the divided IS2; a carrier amplifier (CA) including a first high frequency transistor for amplifying the IS1; a peak amplifier (PA) including a second high frequency transistor and for amplifying the IS2; and an output combination circuit (OCCU) including: a 90-degree phase delay circuit (90DC) formed on a signal line for output of the CA; a combiner for combining output of the 90DC and output of the PA; and an impedance conversion circuit for converting an output impedance of the combiner. The CA and the PA are directly connected to the OCCU without converting an output impedance.

A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source configured input FET and a common gate configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.