A power amplifier with feedback ballast resistance is disclosed. In one aspect, a power amplifier cell may receive a bias signal from a bias circuit where the bias circuit includes a feedback loop having an impedance that, from the perspective of the bias signal is relatively low impedance, but from a ballast thermal control perspective provides sufficient resistance to avoid thermal runaway. In exemplary aspects, this feedback loop may be extended to operate with multiple power amplifier cells and provide differential mode thermal control optimized for individual cell bias signal control and common mode thermal control optimized for thermal control of the collective power amplifier cells of the power amplifier.

An amplifier circuit includes an input terminal used to receive an input signal, an output terminal used to output an output signal, an amplification unit, and a phase adjustment unit. The amplification unit includes an input terminal coupled to the input terminal of the amplifier circuit, an output terminal coupled to the output terminal of the amplifier circuit, a first terminal coupled to a first voltage terminal, and a second terminal coupled to a second voltage terminal. The phase adjustment unit is coupled to the amplification unit. When the amplifier circuit is operated in a first mode, the output signal has a first phase, and when the amplifier circuit is operated in a second mode, the output signal has a second phase. A difference between the first phase and the second phase is within a predetermined range.

A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die.

A a front-end device is arranged to amplify an electric signal from an associated sensor, e.g. for amplifying an electric signal from a neural activity sensor. The front-end device has an amplifier circuit connected between its input and output terminals (Vin, Vout), wherein the amplifier circuit comprises a capacitive-coupled chopper circuit comprising a first gain element and first, second and third chopper switches arranged for operating at a chopper frequency. Further, the amplifier circuit has A) an impedance boosting auxiliary path connected to the input terminal in parallel with a first chopper switch of the CCC, wherein the impedance boosting auxiliary path comprises a pre-charging buffer, and B) a second gain element connected in a feedback path of the CCC. Such front-end device has high input impedance, and the input impedance is uncorrelated with the gain. It is highly suited for implantable micro devices, e.g. brain dusts.

Disclosed is a power amplifier system having a main amplifier with an input coupled to a main radio frequency (RF) input and an output connected to a main RF output, wherein the main amplifier exhibits a nonlinear gain characteristic with compression. At least one compression compensating amplifier has a signal input coupled to the common RF input and a signal output coupled to the common RF output.

Systems, devices, and techniques are described for calibrating a medical device that senses ECAP signals from a patient's nerve tissue. For example a method includes: instructing, with processing circuitry, stimulation circuitry of a medical device to deliver, on stimulation electrodes of the medical device, an electrical stimulation signal having an amplitude substantially equal to zero to a patient; entering, with the processing circuitry subsequent to instructing the stimulation circuitry to deliver the electrical stimulation signal, a passive recharge state on stimulation electrode circuitry; and auto-zeroing, with the processing circuitry, inputs to an operational amplifier of sensing circuitry electrically coupled to sensing electrodes of the medical device while the stimulation electrode circuitry is in the passive recharge state.

A transistor stack can include a combination of floating and body tied devices. Improved performance of the RF amplifier can be obtained by using a single body tied device as the input transistor of the stack, or as the output transistor of the stack, while other transistors of the stack are floating transistors. Transient response of the RF amplifier can be improved by using all body tied devices in the stack.

An amplifying circuit includes a first reconfigurable amplifier configured to selectively operate in a cascode mode or a non-cascode mode, wherein an input of the first reconfigurable amplifier is coupled to a first input of the amplifying circuit, and an output of the first reconfigurable amplifier is coupled to an output of the amplifying circuit. The amplifying circuit also includes a second reconfigurable amplifier configured to selectively operate in the cascode mode or the non-cascode mode, wherein an input of the second reconfigurable amplifier is coupled to a second input of the amplifying circuit, and an output of the second reconfigurable amplifier is coupled to the output of the amplifying circuit.

A local oscillator buffer circuit comprises a complementary common-source stage comprising a first p-channel transistor (MCSP) and a first n-channel transistor (MCSN), arranged such that their respective gate terminals are connected together at a first input node, and their respective drain terminals of each of is connected together at a buffer output node. A complementary source-follower stage comprises a second p-channel transistor (MSFP) and a second n-channel transistor (MSFN), arranged such that their respective gate terminals are connected together at a second input node, and their respective source terminals are connected together at the buffer output node.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.