A radio frequency amplifier includes a transistor, an input impedance matching circuit (e.g., a single-section T-match circuit or a multiple-section bandpass circuit), and a fractional harmonic resonator circuit. The input impedance matching circuit is coupled between an amplification path input and a transistor input terminal. An input of the fractional harmonic resonator circuit is coupled to the amplification path input, and an output of fractional harmonic resonator circuit is coupled to the transistor input terminal. The fractional harmonic resonator circuit is configured to resonate at a resonant frequency that is between a fundamental frequency of operation of the RF amplifier and a second harmonic of the fundamental frequency. According to a further embodiment, the fractional harmonic resonator circuit resonates at a fraction, x, of the fundamental frequency, wherein the fraction is between about 1.25 and about 1.9 (e.g., x≈1.5).

A bias circuit includes a linear core circuit CC with first and second mutually type corresponding transistors (M1; M2) and a current mirror CM with third and fourth transistors (M3; M4) of opposite type of M1 and M2. To obtain an equilibrium with a constant transconductance of the first transistor, first and second negative feedback loops (L1; L2) are applied, one including the linear core circuit CC, the other including the current mirror CM. In a first setting one loop suppresses differences between first and second drain voltages (Vd1; Vd2) and the other loop suppresses differences between one of of the first and second drain voltage Vd1 and Vd2 and a reference voltage Vref. In the second setting, one loop suppresses differences between the first drain voltage Vd1 and the reference voltage Vref and the other loop differences between the second drain voltage Vd2 and the reference voltage Vref.

A local oscillator buffer circuit comprises a complementary common-source stage comprising a first p-channel transistor (MCSP) and a first n-channel transistor (MCSN), arranged such that their respective gate terminals are connected together at a first input node, and their respective drain terminals of each of is connected together at a buffer output node. A complementary source-follower stage comprises a second p-channel transistor (MSFP) and a second n-channel transistor (MSFN), arranged such that their respective gate terminals are connected together at a second input node, and their respective source terminals are connected together at the buffer output node.

A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die.

An amplifier circuit is disclosed. The amplifier circuit includes an input terminal configured to receive an input signal, an output terminal configured to transmit an output signal, and a first signal path including a first amplifying circuit, where the first amplifying circuit is configured to receive the input signal and to transmit a first amplified output to the output terminal, and where the first amplified output includes first amplifier circuit harmonic noise. The amplifier circuit also includes a second signal path including a second amplifying circuit, where the second amplifying circuit receives the input signal and transmits a second amplified output to the output terminal, and where the second amplified output includes second amplifier circuit harmonic noise. The output signal includes the first and second amplified outputs, and the first amplifying circuit harmonic noise is at least partially canceled by the second amplifying circuit harmonic noise in the output signal.

An amplifier device includes an amplifier including cascade-connected power amplifiers in a plurality of stages and a bias circuit configured to supply bias currents to the amplifier. A bias current supplied to a power amplifier in the first stage of the power amplifiers in the plurality of stages exhibits a positive temperature characteristic. A bias current supplied to a power amplifier in the final stage exhibits a negative temperature characteristic.

An amplifier circuit is disclosed. The amplifier circuit includes an input terminal configured to receive an input signal, an output terminal configured to transmit an output signal, and a first signal path including a first amplifying circuit, where the first amplifying circuit is configured to receive the input signal and to transmit a first amplified output to the output terminal, and where the first amplified output includes first amplifier circuit harmonic noise. The amplifier circuit also includes a second signal path including a second amplifying circuit, where the second amplifying circuit receives the input signal and transmits a second amplified output to the output terminal, and where the second amplified output includes second amplifier circuit harmonic noise. The output signal includes the first and second amplified outputs, and the first amplifying circuit harmonic noise is at least partially canceled by the second amplifying circuit harmonic noise in the output signal.

A receiver front end amplifier capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors, and gate to ground capacitors for each leg can be used to further improve the matching performance of the invention.

A MIMO amplifier circuit operable to couple one or more selectable input ports to one or more selectable output ports. The circuit includes N input transistors and M output transistors. Each input transistor has its base coupled to a respective input port node, its emitter coupled to ground, and its collector connected to an intermediate node. Each output transistor has its base coupled to a bias node, its emitter connected to the intermediate node, and its collector coupled to a respective output port nodes. Each input transistor enables the respective input port node when its base is biased. Each output transistor enables the respective output port node when its bias node is asserted. The base of the input transistor for each enabled port is biased to provide a quiescent current I.sub.0*m/n through that input transistor, where m is the number of enabled output ports and n is the number of enabled input ports.

Methods and devices used in mobile receiver front end to support multiple paths and multiple frequency bands are described. The presented devices and methods provide benefits of scalability, frequency band agility, as well as size reduction by using one low noise amplifier per simultaneous outputs. Based on the disclosed teachings, variable gain amplification of multiband signals is also presented.