A microwave amplifier having a load network which provides more efficient amplification of a low power microwave frequency signal. The amplifier comprises a transistor and a load network coupled to the transistor output to shape a waveform of an amplified microwave signal at the transistor current source plane. The load network comprises: a fundamental matching network to provide impedance matching at a fundamental frequency; a half-wave transmission line for a second harmonic frequency disposed between the transistor output and the fundamental matching network; a quarter-wave stub and a five-quarter-wave stub for a third harmonic frequency arranged on the half-wave transmission line to provide an open circuit condition at the third harmonic; and a quarter-wave stub for the second harmonic frequency and a quarter-wave stub for the fundamental frequency, arranged on the half-wave transmission line to provide a short circuit condition at the second harmonic frequency.

A first transistor chip (3) includes a first drain pad (5). A second transistor chip (4) includes a second drain pad (6). A transmission line (9) and a first capacitor (C1) are formed on a resin substrate (1). A first bonding wire (7) connects the first drain pad (5) and one end of the transmission line (9). A second bonding wire (10) connects the second drain pad (6) and one end of the first capacitor (C1). An output terminal (OUT) is connected to the other end of the transmission line (9) and the other end of the first capacitor (C1). A capacitance value of the first capacitor (C1) is selected so as to cause resonance with inductance of the second bonding wire (10).

An amplifier includes a transistor, an input circuit coupled between an amplifier input and a transistor input terminal, and an output circuit coupled between a transistor output and a transistor output terminal. The input circuit includes an input-side harmonic termination circuit with a first inductor and a first capacitance in series between the transistor input terminal and ground. The output circuit includes a second inductor, an output-side harmonic termination circuit, and a shunt-L circuit. The second inductor is coupled between the transistor output terminal and the amplifier output. The output-side harmonic termination circuit includes a third inductor and a second capacitance in series between the amplifier output and ground. The shunt-L circuit includes a fourth inductor and a third capacitance connected in series between the amplifier output and ground. The input-side and output-side harmonic termination circuits resonate at a harmonic frequency of a fundamental frequency of operation of the amplifier.

A stub whose end is connected to an end of a transmission line, and a coupled line disposed in parallel with each of the transmission line and the stub, and electromagnetically coupled to each of the transmission line and the stub are included, and the stub and the coupled line operate as a first resonator for resonating with an odd order harmonic included in the amplified signal, and the transmission line, the stub, and the coupled line operate as a second resonator for resonating with an even order harmonic included in the amplified signal.

A bandpass parametric amplifier circuit includes a plurality of unit cells. At least one unit cell includes a first inductor having a first node coupled to a center conductor and a second node coupled to ground. There is a first capacitor having a first node coupled to the center conductor and a second node coupled to ground. There is a second inductor having a first node coupled to the center conductor. A second capacitor has a first node coupled to a second node of the second inductor. The second capacitor and the second inductor are in series with the center conductor.

Circuits and methods for using in parallel amplification and signal combining are described herein. A circuit uses a digitally controlled multistage cascade combiner, a digital phase and drive signal amplifier controller and a digital combiner controller circuit with N parallel signals with constant amplitudes belonging to an alphabet with M discrete values and discrete phases feeding it. The signals resulting from N power amplifiers (PAs) have also constant amplitudes belonging to an alphabet with N discrete values and discrete phases prior to being fed to the multistage combiner. A digital combiner controller circuit generates digital control information to activate, or deactivate, the outputs of the PAs, where a set of digital control signals generated in digital combiner controller are used to control sets of switches, where the signals can be activated at the combiner's inputs, according to their power and phase values. The digital control information ensures that only in-phase signals are combined in the active combiner stage and any difference among the inputs of the combiners is always minimized. Both digital combiner controller and digital drive signal amplifier controller, share information about the signals not to be fed to the multistage combiner, so that PAs drive signals can also be powered off under these circumstances. In provide high efficiency amplification the signal amplifiers employed before the combining stage may be of switched or current source type.

A method for making a wideband Doherty amplifier with reduced plan width, adapted to transport a radio-frequency signal at a frequency value comprised within a frequency range defined between a minimum frequency value and a maximum frequency value, the amplifier including: a signal source adapted to generate an input signal; a hybrid coupler or a splitter network adapted to receive the input signal and divide it into first and second output signals phase-shifted by 90°; a carrier amplifier adapted to receive as input the first output signal; a peak amplifier adapted to receive as input the second output signal; an output network arranged between the carrier and peak amplifiers and a delivery node adapted to be connected to a load, the output network including a recombination node adapted to receive the signals output by the carrier amplifier and the peak amplifier, and a transmission line implemented as a printed circuit track applied to an insulating substrate, wherein capacitors are inserted on the track which are adapted to compensate for the non-ideality characteristics of the semiconductor used for making the line.

A front-end module of a wireless device can replace a passive duplexer with an active duplexer that uses metamaterial matching circuits. The active duplexer can be formed from a power amplifier circuit and a low noise amplifier circuit that each include a metamaterial matching circuit. The combination of a power amplifier circuit and a low noise amplifier circuit that each utilize metamaterials to form the associated matching circuit can provide the functionality of a duplexer without including the additional circuitry of a stand-alone or passive duplexer. Thus, in certain cases, the front-end module can provide duplexer functionality without including a separate duplexer. Advantageously, in certain cases, the size of the front-end module can be reduced by eliminating the passive duplexer. Further, the loss introduced into the signal path by the passive duplexer is eliminated improving the performance of the communication system that includes the active duplexer.

A first transmission line and a second transmission line that are connected in series to each other are disposed at different positions in a thickness direction of a substrate. A third transmission line is disposed between the first transmission line and the second transmission line in the thickness direction of the substrate. The third transmission line includes a first end portion connected to one end portion of the first transmission line, and a second end portion that is AC-grounded. The first transmission line and the second transmission line are electromagnetically coupled to the third transmission line.

Power amplifier apparatuses and techniques for optimizing the design of power amplifiers are disclosed. In one aspect, a method for optimizing a power amplifier includes selecting a circuit topology for the power amplifier. The circuit topology includes one or more photoconductive switches and an impedance matching network including one or more parameter values representative of the impedance matching network or the photoconductive switches that can be adjusted. The method further includes selecting one or more optimization goals for the impedance matching network and the one or more photoconductive switches, and adjusting the one or more parameter values according to the one or more optimization goals. The one or more optimization goals include an efficiency at a particular power output.