An output buffer circuit for avoiding voltage overshoot includes an input stage, an output bias circuit, an output stage, a clamp circuit, and a control unit. The input stage includes a positive input terminal, for receiving an input voltage, and a negative input terminal. The input stage generates a current signal according to the input voltage. The output bias circuit is coupled to the input stage, for generating a dynamic bias according to the current signal. The output stage is coupled to the input stage and the output bias circuit, including an output terminal, reversely coupled to the positive input terminal, and at least one output transistor, coupled to the output bias circuit and the output terminal, for providing a driving current to the output terminal according to the dynamic bias to generate an output voltage.

Methods and devices for limiting the power level of low noise amplifiers (LNA) implemented in radio frequency (RF) receiver front-ends. The described methods are applicable to bypass, low and high gain modes of the LNA. According to the described methods, the decoder allows the signal to be clamped before or after being attenuated. The benefit of such methods is to improve large signal performances (e.g. IIP3, P1dB) of the RF receiver front-end, while still meeting the clamping requirements, or improve (lower) clamped output power, while still meeting large signal performances (e.g. IIP3, P1dB).

Embodiments of this application disclose a trans-impedance amplifier and a trans-impedance amplifier control method that are used in the field of circuit technologies. A trans-impedance amplifier TIA includes an inverting amplification circuit and a voltage clamping circuit. The inverting amplification circuit is connected in parallel to the voltage clamping circuit. The inverting amplification circuit includes a first PMOS transistor and a first NMOS transistor that have a common gate. A source of the first PMOS transistor is connected to a drain of the first NMOS transistor. The voltage clamping circuit includes a second PMOS transistor and a second NMOS transistor that have a common gate. Gates of the two transistors are connected to an input end of the TIA. A source of the second NMOS transistor and a drain of the second PMOS transistor are connected to an output end of the TIA.

The present disclosure discloses a gate voltage control circuit of an IGBT and a control method thereof. The gate voltage control circuit of the IGBT comprises a voltage control circuit, an active clamping circuit and a power amplifier circuit. A control voltage outputted by the voltage control circuit indirectly controls a gate voltage of the IGBT, so as to achieve a better control of the gate voltage of the IGBT with a smaller loss. It may prevent the active clamping circuit from a too-early response and may increase the active clamping circuit response speed; and may avoid the voltage oscillation of the collector-emitter voltage Vce and the gate voltage Vge, and may improve the reliability of the IGBTs connected in series.

Various methods and circuital arrangements for protection of a power amplifier (PA) from high input power conditions are presented. According to one aspect, a protection circuit coupled to a stage of the PA limits a current through the stage during the high input power conditions. Limiting of the current is provided by a current limiter circuit that includes a current generator coupled to a current mirror. The current is limited to a high value that is based on a reference current generated by the current generator. In one aspect, the reference current is programmable or variable. In another aspect the protection circuit includes a clamp that limits a low voltage at an output of the current limiter circuit. In another aspect, the protection circuit includes a pre-charge circuit that pre-charges the output of the current limiter circuit. In another aspect a filter is embedded within the current limiter circuit.

Circuits and methods for suppression of negative transient voltage may be implemented in systems that combine high-speed data, audio, and charging at a plug. The circuits and methods for suppression of the negative transient voltage may include a first diode and transistor coupled in series between a pin and ground, where the transistor is controlled by an output of a voltage comparator that is also coupled to the first pin. A negative transient voltage event may cause the comparator to activate the transistor to sink a current through the diode.

One embodiment is an apparatus including a detector circuit electrically coupled between a signal source and a second circuit, the signal source generating a first signal, the detector circuit detecting a level of the first signal and generating a first control signal when the detected level of the first signal exceeds a first threshold value, and a clamping switch electrically coupled to receive the first control signal from the detector circuit, the clamping switch including a multi-terminal active device. The first control signal controls a state of the clamping switch such that the clamping switch clamps a level of a signal applied to the second circuit when the level of the first signal exceeds the first threshold value.

The present disclosure discloses a gate voltage control circuit of an IGBT and a control method thereof. The gate voltage control circuit of the IGBT comprises a voltage control circuit, an active clamping circuit and a power amplifier circuit. A control voltage outputted by the voltage control circuit indirectly controls a gate voltage of the IGBT, so as to achieve a better control of the gate voltage of the IGBT with a smaller loss. It may prevent the active clamping circuit from a too-early response and may increase the active clamping circuit response speed; and may avoid the voltage oscillation of the collector-emitter voltage Vce and the gate voltage Vge, and may improve the reliability of the IGBTs connected in series.

Base station antennas utilize RF transmitters and receivers, which operate with enhanced bias control to achieve very high speed switching during TDD operation. A radio frequency communication circuit for TDD includes a transmit/receive amplifier (e.g., MMIC) having first and second input terminals, which are responsive to a bias control voltage and radio frequency input signal. A bias control circuit is provided, which is electrically coupled to the first input terminal and a current receiving terminal of the transmit/receive amplifier. The bias control circuit includes a closed-loop feedback path between the current receiving terminal and the first input terminal, which is configured to regulate a magnitude of the bias control voltage with high precision to thereby achieve a substantially constant quiescent bias current at the current receiving terminal when the transmit/receive amplifier is enabled.

Circuitry for driving first and second loads, the circuitry comprising: a first output signal path for supplying a first driving signal to the first load; a second output signal path for supplying a second driving signal to the second load; sequencer circuitry configured to initiate a first state change in the first output signal path and a second state change in the second output signal path, wherein the sequencer circuitry is configured to control the initiation of the first and second state changes such that the second state change is not synchronised with the first state change.