Equalizing an input signal according to a receiver equalizer peaking circuit having a capacitor FET (CFET) providing a capacitive value and a resistor FET (RFET) providing a resistive value, generating a capacitor control voltage at a gate of the CFET using a capacitor controller DAC based on a first reference voltage, and a RFET control voltage at a gate of the RFET using a resistor controller DAC based on a second reference voltage, generating the first reference voltage using a replica input FET, the first reference voltage varying according to a threshold voltage (Vt) of an input FET, providing the first reference voltage to the capacitor controller DAC, generating the second reference voltage using a replica RFET, the second reference voltage varying with respect to the first reference voltage and a Vt of the replica of the RFET, and providing the second reference voltage to the resistor controller DAC.

Apparatus and methods for LNAs with mid-node impedance networks are provided herein. In certain configurations, an LNA includes a mid-node impedance circuit including a resistor and a capacitor electrically connected in parallel, a cascode device electrically connected between an output terminal and the mid-node impedance circuit, and a transconductance device electrically connected between the mid-node impedance circuit and ground. The transconductance device amplifies a radio frequency signal received from an input terminal. The LNA further includes a feedback bias circuit electrically connected between the output terminal and the input terminal and operable to control an input bias voltage of the transconductance device.

A multi-mode envelope tracking (ET) amplifier circuit is provided. The multi-mode ET amplifier circuit can operate in a low-resource block (RB) mode, a mid-RB mode, and a high-RB mode. The multi-mode ET amplifier circuit includes fast switcher circuitry having a first switcher path and a second switcher path and configured to generate an alternating current (AC) current. A control circuit activates the fast switcher circuitry in the mid-RB mode and the high-RB mode, while deactivating the fast switcher circuitry in the low-RB mode. More specifically, the control circuit selectively activates one of the first switcher path and the second switcher path in the mid-RB mode and activates both the first switcher path and the second switcher path in the high-RB mode. As a result, it is possible to improve efficiency of ET tracker circuitry and the multi-mode ET amplifier circuit in all operation modes.

Device and method are disclosed for downlink gain compensation at a radio unit. According to an embodiment, the device comprises a pre-distortion circuit, a digital gain adjuster, a gain determiner and a first gain controller. The pre-distortion circuit is configured to generate and apply a pre-distortion to an input signal. The digital gain adjuster is configured to apply an adjustable gain to an output signal from the pre-distortion circuit. The gain determiner is configured to determine a gain difference between a target downlink gain and current downlink gain. The first gain controller is configured to control the digital gain adjuster based on the gain difference. A radio unit comprising the device is also disclosed.

An operational amplifier includes a differential amplification circuit configured to receive and amplify an input voltage to generate an output voltage, and receive a feedback signal, and the feedback signal adjusts a common-mode voltage of the output voltage, a reference voltage generation circuit configured to detect status information of the operational amplifier, and generate a reference voltage based on the status information, where the status information includes a temperature or an operating voltage of the operational amplifier, and a common-mode feedback circuit configured to receive the output voltage and the reference voltage, and provide the feedback signal to the differential amplification circuit based on the output voltage and the reference voltage.

This application is directed to methods and devices for an efficient power amplification system. An electronic device includes a first and a second power amplifier that are coupled to a quadrature combiner, a temperature monitoring circuit coupled to the first and second power amplifiers, and a controller coupled to the temperature monitoring circuit. The temperature monitoring circuit is configured to determine a temperature difference between the first and second power amplifiers. The controller is configured to adjust operation of at least one of the first and second power amplifiers to reduce the temperature difference between the first and second power amplifiers.

A power amplifier module includes a power amplifier including an amplifier including an amplifying transistor configured to amplify an input signal, and output an output signal, and a bias circuit including a bias transistor configured to provide a bias current to the amplifying transistor; and a controller configured to provide a control current to the bias transistor, wherein the controller is configured to vary the control current based on a temperature of the amplifying transistor.

In a semiconductor module, a first conductive portion is raised on a lower surface of a first member to which a second member including a semiconductor element and being smaller than the first member in plan view is joined. A second conductive portion is raised at the second member in the same direction as the first conductive portion. The first and second members are mounted on a module substrate with the interposed first and second conductive portions. A sealing material is disposed on a mounting surface of the module substrate, while covering at least an area of the first member. The sealing material has a top surface facing in the same direction as the top surface of the first member and side surfaces connected to its top surface. A metal film is disposed on the top and side surfaces of the sealing material and side surfaces of the module substrate.

An amplifier includes an input circuit that amplifies a difference between a first input voltage and a second input voltage to generate a first current and a second current. A positive feedback circuit amplifies a difference between the first current and the second current to generate a third current and a fourth current and outputs a difference between the third current and the fourth current through an output node. A temperature compensation circuit adjusts an amplification factor of the positive feedback circuit in response to a change of temperature.

There is provided a device that includes a MOS transistor and a bias circuit coupled to the MOS transistor. The bias circuit is configured to bias the MOS transistor thereby maintaining the MOS transistor outside of saturation. The MOS transistor is configured to operate as a buffer or an amplifier, while being outside of saturation.