An electronic device may include: at least one communication processor, an RFIC, at least one power amplifier , and at least one converter and wherein the at least one communication processor is configured to: set a driving voltage, to be applied to a first power amplifier for amplifying a first RF signal provided from the RFIC among the at least one power amplifier, to be a first voltage, based on an APT mode, control at least part of the at least one converter to provide a first voltage, set based on the APT mode, to the first power amplifier during a transmission period of the first RF signal, and control at least part of the at least one converter to provide the first voltage to the first power amplifier during at least partial period of a remaining period in which no RF signal is transmitted, based on the occurrence of an event associated with audible noise.

A Doherty power amplifier comprising: an input configured to receive an input signal to be amplified and to split the input signal into a first portion and a second portion, the input signal having an operating frequency; a carrier amplifier path coupled to the input to receive the first portion, the carrier amplifier path including a carrier amplifier coupled to a differential inverter, the carrier amplifier being configured to amplify the first portion and provide an amplified first portion to the differential inverter, the differential inverter having a capacitance configured to make the differential inverter behave as a short circuit at odd harmonics of the operating frequency, the capacitance coupling a first path and a second path of the differential inverter in parallel; and a peaking amplifier path coupled to the input to receive the second portion and comprising a peaking amplifier configured to amplify the second portion.

Integrated circuits, such as power amplifier integrated circuits, are disclosed containing compact-footprint, vertically-integrated capacitor-avalanche diode (AD) structures. In embodiments, the integrated circuit includes a semiconductor substrate, a metal layer system, and a vertically-integrated capacitor-AD structure. The metal layer system includes, in turn, a body of dielectric material in which a plurality of patterned metal layers are located. The vertically-integrated capacitor-AD structure includes a first AD formed, at least in part, by patterned portions of the first patterned metal layer. A first metal-insulator-metal (MIM) capacitor is also formed in the metal layer system and at least partially overlaps with the first AD, as taken along a vertical axis orthogonal to the principal surface of the semiconductor substrate. In certain instances, at least a majority, if not the entirety of the first AD vertically overlaps with the first MIM capacitor, by surface area, as taken along the vertical axis.

Fast envelope tracking systems are provided herein. In certain embodiments, an envelope tracking system for a power amplifier includes a switching regulator and a differential error amplifier configured to operate in combination with one another to generate a power amplifier supply voltage for the power amplifier based on an envelope of a radio frequency (RF) signal amplified by the power amplifier. The envelope tracking system further includes a differential envelope amplifier configured to amplify a differential envelope signal to generate a single-ended envelope signal that changes in relation to the envelope of the RF signal. Additionally, the differential error amplifier generates an output current operable to adjust a voltage level of the power amplifier supply voltage based on comparing the single-ended envelope signal to a reference signal.

Disclosed is an amplifying circuit and method. In one embodiment, an amplifying circuit, includes: a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein source terminal and body terminal of the first transistor is coupled together through a first resistor.

A power amplifier circuit includes a current generator and a current mirror driver. The current generator has a first input connected to a first voltage supply and an output configured to generate a first current. The current generator includes a first transistor, a second transistor, a first resistor and a second resistor. The first transistor has an emitter connected to ground. The second transistor has a base connected to a base of the first transistor and an emitter connected to ground. The first resistor is connected between the first voltage supply and a collector of the first transistor. The second resistor is connected between the first voltage supply and a collector of the second transistor. The current mirror drive has a first input connected to the output of the current generator to receive the first current and an output configured to generate a second current.

A power supply switch circuit includes a switch circuit including a first switch configured to switch a first power source voltage to a power supply terminal of a power amplifier, and a second switch configured to switch a second power source voltage to the power supply terminal; a switch controller configured to control the switch circuit; and a power supply circuit configured to supply a third power source voltage to the power supply terminal when a first voltage of the power supply terminal is lower than a predetermined second voltage.

A semiconductor device includes a substrate, an active region provided in the substrate, a plurality of gate fingers provided on the active region, extending in an extension direction, and arranged in an arrangement direction orthogonal to the extension direction, and a gate connection wiring commonly connected to the plurality of gate fingers and provided between the plurality of gate fingers and a first side surface of the substrate, wherein when viewed from the arrangement direction, a first position where a first end of a first gate finger as a part of the plurality of gate fingers is connected to the gate connection wiring is closer to the first side surface than a second position where a first end of a second gate finger as another part of the plurality of gate fingers is connected to the gate connection wiring.

A circuit includes a field effect transistor (FET), a reference transistor having an output coupled to an output of the FET, an active bias circuit coupled to the reference transistor and configured to generate an input signal for the reference transistor in response to a change in drain current of the reference transistor due to carrier trapping and to apply the input signal to an input of the reference transistor, and a summing node coupled to an input of the FET and to the input of the reference transistor. The summing node adds the input signal to an input signal of the FET to compensate the carrier trapping effect.

An antenna controller for an antenna is configured to request and receive status information comprising power amplifier data of at least two adjustable power amplifiers. The antenna controller is configured to determine at least one target setting for the at least two adjustable power amplifiers based on the received power amplifier data, and to send the at least one target setting for the at least two adjustable power amplifiers. Hereby it is made possible for an antenna controller to set an overall target for multiple adjustable power amplifiers of the antenna. This in turn makes it possible to make the settings for the adjustable power amplifiers such that the transmission signal becomes linearized by a shared digital pre-distorter when transmitting using the multiple adjustable power amplifiers of the antenna. A Radio Frequency Integrated Circuit controller for an antenna subarray is configured to control at least one adjustable power amplifier.