The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.

A light receiving unit receives a pulsed optical signal arriving from a search region. A branching unit generates, from a received light signal, a plurality of branch signals having signal intensities proportional to a signal intensity of the received light signal and different from one another. A conversion unit converts, from analog to digital, a signal fed via the individual path selected by a selection unit, and in accordance with a result of the conversion, a processing unit generates information regarding an object reflecting the optical signal. A control unit causes the selection unit to select one of the individual paths for which a determination unit determines that a magnitude of the fed signal is within an input range of the conversion unit and which provides the highest gain.

A multi-level voltage circuit and related apparatus are provided. The multi-level voltage circuit is configured to provide an average power tracking (APT) voltage to an amplifier circuit for amplifying a radio frequency (RF) signal, which can be modulated in a number of orthogonal frequency division multiplexing (OFDM) symbols. The RF signal may experience power fluctuations from one OFDM symbol to another and the multi-level voltage circuit may need to adjust the APT voltage accordingly. In examples discussed herein, when the APT voltage needs to increase from a present value to a higher future value at a predetermined effective time, the multi-level voltage circuit may start increasing the APT voltage from the present value toward the future value ahead of the predetermined effective time. As such, it may be possible to ramp up the APT voltage in a timely fashion to help improve linearity and efficiency of the amplifier circuit.

The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode Voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.

An apparatus for controlling the gain and phase of an input signal input to a power amplifier comprises a gain control loop configured to control the gain of the input signal based on power levels of the input signal and an amplified signal output by the power amplifier, to obtain a predetermined gain of the amplified signal, and a phase control loop configured to obtain an error signal related to a phase difference between a first signal derived from the input and a second signal derived from the amplified signal, and control the phase based on the error signal, to obtain a predetermined phase of the amplified signal. The phase control loop delays the first signal such that the delayed first signal and the second signal used to obtain the error signal correspond to the same part of the input signal. The apparatus may be included in a satellite.

The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.

A variable-gain power amplifying technique includes generating, with a network of one or more reactive components included in an oscillator, a first oscillating signal, and outputting, via one or more taps included in the network of the reactive components, a second oscillating signal. The second oscillating signal has a magnitude that is proportional to and less than the first oscillating signal. The power amplifying technique further includes selecting one of the first and second oscillating signals to use for generating a power-amplified output signal, and amplifying the selected one of the first and second oscillating signals to generate the power-amplified output signal.

A variable gain amplifier (1) includes: a signal transmission circuit (10, 20) including amplifying transistor units (11.sub.1 to 11.sub.N, and 21.sub.1 to 21.sub.N) connected in parallel between a signal input port (2P, 2N) and a signal output port (3P, 3N); a load circuit (40) connected between a supply line of power supply voltage (VDD) and an output end of the signal transmission circuit (10, 20); a signal short circuit (30) including a short-circuit transistor unit (31) connected between the supply line of the power supply voltage (VDD) and an input end of the signal transmission circuit (10, 20), a constant-current source circuit (42), and a transistor control circuit (46). The transistor control circuit (46) selects transistor units to be turned on, from among the amplifying transistor units (11.sub.1 to 11.sub.N, and 21.sub.1 to 21.sub.N) and the short-circuit transistor unit (31), and supplies control voltages for turning on the selected transistor units.

An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals.

A variable-gain power amplifying technique includes generating, with a network of one or more reactive components included in an oscillator, a first oscillating signal, and outputting, via one or more taps included in the network of the reactive components, a second oscillating signal. The second oscillating signal has a magnitude that is proportional to and less than the first oscillating signal. The power amplifying technique further includes selecting one of the first and second oscillating signals to use for generating a power-amplified output signal, and amplifying the selected one of the first and second oscillating signals to generate the power-amplified output signal.