The detection matrix for an Orthogonal Differential Vector Signaling code is typically embodied as a transistor circuit with multiple active signal inputs. An alternative detection matrix approach uses passive resistor networks to sum at least some of the input terms before active detection.

Disclosed herein is a voltage gain amplifier for use in an automotive radar receiver chain. The voltage gain amplifier utilizes pole-zero cancelation to yield a desired transfer function without gain peaking at a bandwidth in which attenuation is desired, and utilizes a low pass filter effectively formed by a feedback loop including a high pass filter and a differential amplifier to ensure the desired level of attenuation at the desired bandwidth. In some instances, a chopper may be utilized in the feedback loop prior to the high pass filter, and after the differential amplifier, so as to reduce the bandwidth of the differential amplifier in the feedback loop.

A signal gain determination circuit including a digital comparator, a digital controller and an arithmetic module, and a signal gain determination method are provided. A sensing integration circuit generates a first count during a first integration time according to a first sensing signal. The digital comparator compares the first count and a predetermined count to generate a comparison result. The digital controller generates a control signal for indicating a signal gain to a signal amplifier of the sensing integration circuit according to the comparison result. The signal amplifier adjusts the first sensing signal according to the signal gain to generate a second sensing signal, so that the sensing integration circuit generates a second count corresponding to the second sensing signal during a second integration time. The arithmetic module generates an output count corresponding to the first sensing signal according to the second count and the signal gain.

A transimpedance amplifier circuit includes an amplifier circuit that converts a current signal into a voltage signal with a gain being varied based on a control signal and a gain control circuit that generates the control signal based on an amplitude of the voltage signal. The gain control circuit includes a detection circuit that generates an amplitude-detection-signal in accordance with the amplitude of the voltage signal, a setting circuit that generates an amplitude-reference-signal, a differential voltage generation circuit that generates a differential-voltage-signal obtained by offsetting a voltage difference between the amplitude-detection-signal and the amplitude-reference-signal based on an amplitude-setting-signal, an operational transconductance amplifier (OTA) that generates a differential-current-signal based on the differential-voltage-signal, and a variable capacitor circuit having a variable capacitance being varied based on the amplitude-setting-signal, and configured to be charged/discharged by the differential-current-signal and output a charging voltage. The control signal is generated based on the charging voltage.

In one embodiment, an apparatus includes: a low noise amplifier (LNA) to receive and amplify a radio frequency (RF) signal, the LNA having a first controllable gain; a mixer to downconvert the RF signal to a second frequency signal; a programmable gain amplifier (PGA) coupled to the mixer to amplify the second frequency signal, the PGA having a second controllable gain; a digitizer to digitize the second frequency signal to a digitized signal; a demodulator coupled to the digitizer to demodulate the digitized signal; an automatic gain control (AGC) circuit to control one or more of the first controllable gain and the second controllable gain; and an AGC settling circuit to cause the demodulator to begin operation in response to determining that the AGC circuit has settled.

A digitally controlled analog filter device. The digitally controlled analog filter device includes one or more digitally controlled analog signal amplifiers. The digitally controlled analog signal amplifiers are configured to have a gain of the digitally controlled analog signal amplifiers controlled by digital signals. The digitally controlled analog filter device further includes one or more analog time delay circuits coupled to signal input nodes of the digitally controlled analog signal amplifiers. The analog time delay circuits are configured to implement an analog signal delay. The digitally controlled analog filter device further includes a digital closed loop control circuit coupled to the digitally controlled analog signal amplifiers to digitally control the gain of the digitally controlled analog signal amplifiers.

The disclosure relates to technology for power supply for a voltage controller oscillator (VCO). A peak detector circuit determines the amplitude of the output for the VCO, which is compared to a reference value in an automatic gain control loop. An input voltage for the VCO is determined based on a difference between the reference value and the output of the peak detector circuit. The peak detector circuit can be implemented using parasitic bipolar devices in an integrated circuit formed in a CMOS process.

Disclosed herein are methods for use in operating signal amplifiers that provide impedance adjustments for different gain modes. The impedance adjustments are configured to result in a constant real impedance for an input signal at the amplifier. Some of the disclosed methods adjust impedance using switchable inductors to compensate for changes in impedance with changing gain modes. Some of the disclosed methods adjust a device size to compensate for changes in impedance with changing gain modes. By providing impedance adjustments, the amplifiers reduce losses and improve performance by improving impedance matching over a range of gain modes.

An asymmetric signal path approach is used to extract differential signals out of the photodetector (e.g., a photodiode) for amplification by a differential transimpedance amplifier (TIA). This asymmetric-path differential TIA configuration has less low-frequency Inter Symbol Interference (ISI) (also known as Baseline Wander), less high-frequency noise amplification, and higher bandwidth capabilities. There is no power penalty with this design in comparison to a single-ended TIA, can extend the range of the link for a given system power consumption, and can decrease transmitter power for a given range.

An amplifier circuit includes an amplifier for generating an amplified input signal according to an input signal, and an attenuator circuit coupled to the amplifier. The attenuator circuit includes an input terminal for receiving the input signal or the amplified input signal, an output terminal, a reference voltage terminal, a zeroth resistor-switch circuit, a first resistor-switch circuit, and a second resistor-switch circuit. The zeroth resistor-switch circuit includes a first terminal coupled to the input terminal, a second terminal coupled to the output terminal, a zeroth switch coupled to the first terminal of the zeroth resistor-switch circuit and the second terminal of the zeroth resistor-switch circuit, a zeroth resistor coupled between the first terminal of the zeroth resistor-switch circuit and the second terminal of the zeroth resistor-switch circuit, a first resistor coupled between the zeroth resistor and the second terminal of the zeroth resistor-switch circuit, and a first switch.