A novel and useful discrete time IIR bandpass filter is disclosed that takes advantage of clock phase reuse thereby leading to significant improvements in filtering, especially stop band rejection in comparison to prior art filters. The bandpass filter of the present invention achieves improved filtering performance without adding any additional clock phases to the circuit. In particular, reuse of the already existing clock phases increases the order and performance of the filter. The invention exploits reuse of the clock phases to provide higher order filtering along with a discrete time IIR filter design which is capable of operating at high frequency. Consequently, much better filtering is achieved and the quality factor of the filter is improved leading to sharper transition bands especially for close-in band blockers in modern 4G/5G receivers.

A switched capacitor circuit includes an output capacitor, a first transmission switch, a first reference buffer, a second transmission switch, a second reference buffer and a charge compensation circuit. The output capacitor includes a first terminal and a second terminal, wherein the first terminal is coupled to an output terminal of the switched capacitor circuit, and the second terminal is coupled to a reference node. The first transmission switch is coupled to the reference node. The first reference buffer is coupled to the first transmission switch. The second transmission switch is coupled to the reference node. The second reference buffer is coupled to the second transmission switch. The charge compensation circuit is coupled to the reference node.

A FIR filter (15), comprising an input terminal for receiving an input signal, a first filtering circuit comprising: a first transconductance device (30a) configured to generate a first current signal (i1) proportional to the input signal; a first analog switch (41a) commuted in n by a first digital gate signal (ϕ1) and configured to block the current signal when the first digital gate signal has a first value and to transmit the current signal to a first integrating capacitor (45a) when the first digital gate signal has a second value; characterized in that the first digital gate signal (ϕ1) comprises a periodic series of pulses, wherein the pulses have widths proportional to the filter coefficients.

A sensor device includes: first sensors; second sensors which form capacitances with the first sensors; a sensor transmitter connected to the first sensors, where the sensor transmitter supplies driving signals to the first sensors; and a sensor receiver connected to the second sensors, where the sensor receiver receives sensing signals from the second sensors, and the sensor receiver includes a band pass filter which filters the sensing signals. The band pass filter includes: a first integrator including a first amplifier; a first high pass filter converter connected to a first input terminal, a second input terminal and a first output terminal of the first amplifier, where the first high pass filter converter time-divisionally provides N high pass filter conversion paths; and a first gain auxiliary component connected to the first input terminal and the first output terminal of the first amplifier while the first integrator performs an integral function.

An adaptive capacitive filter circuit includes: a first terminal adapted to be coupled to a rectifier bridge output; a second terminal adapted to be coupled to a ground terminal; a first capacitor having a first electrode and a second electrode, the first electrode of the first capacitor coupled to the first terminal; a second capacitor having a first electrode and a second electrode, the second electrode of the second capacitor coupled to the second terminal; a first switch coupled between the second electrode of the first capacitor and the second terminal; a second switch coupled between the first terminal and the first electrode of the second capacitor; and a third switch coupled between the second electrode of the first capacitor and the first electrode of the second capacitor.

A variable circuit includes a switch including a plurality of input terminals and a plurality of output terminals and an external wiring line. The multiple input terminals include a first input terminal to which a first input signal is inputted and a second input terminal to which a second input signal is inputted. The multiple output terminals include a first output terminal from which a first output signal is outputted and a second output terminal from which a second output signal is outputted. The switch is capable of forming at least one internal connection path electrically connecting any one of the multiple input terminals and any one of the multiple output terminals. The external wiring line is disposed outside the switch and is configured to electrically connect the second output terminal to the second input terminal.

An apparatus includes a differential current-to-voltage conversion circuit that includes an input sampling stage circuit, a differential integration and DC signal cancellation stage circuit, and an amplification and accumulator stage circuit. An input common mode voltage of the differential current-to-voltage circuit is independent of an output common mode voltage of the differential current-to-voltage circuit.

A PFM control circuit includes a switching circuit, a slope-decision circuit, a flip-flop, a first and a second comparison circuits. The first comparison circuit outputs a first signal according to an output voltage of a power conversion circuit. The switching circuit outputs a switching signal according to an output current of the power conversion circuit. The slope-decision circuit outputs a slope modulation voltage, and determines a slope modulation voltage with a first or a second slope according to the switching signal. The second comparison circuit outputs the second signal according to the slope modulation voltage. The flip-flop outputs a control signal to the power conversion circuit according to the first and the second signals. When the slope modulation voltage has the first or the second slope, the control signal has a first or a second frequency accordingly. The first frequency is higher than the second frequency.

Tunable delay circuit devices have an input port, an output port, at least three parallel paths connecting the input port and the output port, on each path, an input switch and an output switch, and on each path, a plurality of shunt resonant tanks connected between the input switch and the output switch, each shunt resonant tank periodically chargeable from the input port and dischargeable to the output port by operation of the input switch and the output switch.

An adaptive capacitive filter circuit includes: a first terminal adapted to be coupled to a rectifier bridge output; a second terminal adapted to be coupled to a ground terminal; a first capacitor having a first electrode and a second electrode, the first electrode of the first capacitor coupled to the first terminal; a second capacitor having a first electrode and a second electrode, the second electrode of the second capacitor coupled to the second terminal; a first switch coupled between the second electrode of the first capacitor and the second terminal; a second switch coupled between the first terminal and the first electrode of the second capacitor; and a third switch coupled between the second electrode of the first capacitor and the first electrode of the second capacitor.