Some embodiments include apparatus and methods using a first ring oscillator, a second ring oscillator, and circuit coupled to the first and second ring oscillators. The first ring oscillator includes a first memory cell and a first plurality of stages coupled to the first memory cell. The second ring oscillator includes a second memory cell and a second plurality of stages coupled to the second memory cell. The circuit includes a first input node coupled to an output node of the first ring oscillator and a second input node coupled to an output node of the second ring oscillator. In one of such embodiments, the circuit can operate to generate identification information to authenticate the apparatus.

A processing system includes a pseudo-random bit sequence (PRBS) control unit and a PRBS generator that is used to dynamically generate a PRBS from, for example, a first PRBS and a second PRBS. The PRBS generator is coupled to the PRBS control unit. The PRBS generator generates the second PRBS by dynamically adjusting from a first set of flip-flops of a master set of flip-flops that generate the first PRBS to a second set of flip-flops of the first master set of flip-flops that generate the second PRBS. The PRBS generator includes a plurality of PRBS logic engines coupled to a first PRBS multiplexer, the first PRBS multiplexer being used to select either the first PRBS or the second PRBS that is output by the PRBS generator.

A processing system includes a pseudo-random bit sequence (PRBS) control unit and a PRBS generator that is used to dynamically generate a PRBS from, for example, a first PRBS and a second PRBS. The PRBS generator is coupled to the PRBS control unit. The PRBS generator generates the second PRBS by dynamically adjusting from a first set of flip-flops of a master set of flip-flops that generate the first PRBS to a second set of flip-flops of the first master set of flip-flops that generate the second PRBS. The PRBS generator includes a plurality of PRBS logic engines coupled to a first PRBS multiplexer, the first PRBS multiplexer being used to select either the first PRBS or the second PRBS that is output by the PRBS generator.

At least some aspects of the present disclosure provide for a system. In some examples, the system includes a pulse width modulation (PWM) generator configured to generate a PWM signal. The PWM generator generates the PWM signal by generating a first signal having a first dithering profile and a first frequency bandwidth, generating a second signal having a second dithering profile and a second frequency bandwidth greater than the first frequency bandwidth, modulating the second signal with the first signal to generate a dual random spread spectrum signal, and generating the pulse width modulation signal according to the dual random spread spectrum signal.

Disclosed herein are three context-aware architectures to accelerate the three state-of-the-art deterministic methods of SC. The proposed designs employ a control unit to extract the minimum bit-width required to precisely represent each input data. The lengths of bit-streams are reduced to the minimum lengths required to precisely represent each input data. The noise-tolerance property of the designs is preserved as each bit-flip can only introduce a least significant bit error. The proposed designs achieve a considerable improvement in the processing time at a reasonable hardware cost overhead. The proposed designs make the deterministic bit-stream processing more appealing for applications that expect highly accurate computation and also for error-tolerant applications.

Disclosed herein are three context-aware architectures to accelerate the three state-of-the-art deterministic methods of SC. The proposed designs employ a control unit to extract the minimum bit-width required to precisely represent each input data. The lengths of bit-streams are reduced to the minimum lengths required to precisely represent each input data. The noise-tolerance property of the designs is preserved as each bit-flip can only introduce a least significant bit error. The proposed designs achieve a considerable improvement in the processing time at a reasonable hardware cost overhead. The proposed designs make the deterministic bit-stream processing more appealing for applications that expect highly accurate computation and also for error-tolerant applications.

A true random number generator device based on a diffusive memristor is disclosed. The random number generator device includes a diffusive memristor driven by a pulse generator circuit. The diffusive memristor produces a stochastically switched output signal. A comparator circuit receives the stochastically switched output signal from the diffusive memristor and generates an output signal having a random pulse width. An AND gate logic circuit is driven by a clock signal and the output signal from the comparator circuit. The AND gate logic circuit produces a combined output signal. A counter circuit receives the combined output signal from the AND gate logic circuit and generates a random bit string output signal.

A true random number generator device based on a diffusive memristor is disclosed. The random number generator device includes a diffusive memristor driven by a pulse generator circuit. The diffusive memristor produces a stochastically switched output signal. A comparator circuit receives the stochastically switched output signal from the diffusive memristor and generates an output signal having a random pulse width. An AND gate logic circuit is driven by a clock signal and the output signal from the comparator circuit. The AND gate logic circuit produces a combined output signal. A counter circuit receives the combined output signal from the AND gate logic circuit and generates a random bit string output signal.

A digital transceiver is provided. The digital transceiver includes a clock generator configured to generate a first clock signal having a first frequency of a fixed value and a transmitter driven by the first clock signal of the first frequency to transmit data. Additionally, the digital transceiver includes an inverter coupled to the clock generator to generate an inverted first clock signal of the first frequency. Further, it includes a frequency detector configured to compare the first frequency with a second frequency of a feedback signal in a loop of feedback to determine a frequency control word F. Furthermore, it includes a digitally-controlled oscillator driven by the frequency control word F in the loop of feedback to output a second clock signal with a time-average frequency substantially synchronous to the first frequency with a boundary spread and a receiver driven by the second clock signal to receive the data.

Random number generator (GL) comprising adjustable speed ring oscillators (GPRS, GPRS′), which have outputs (o-GPRS, o-GPRS′) connected to inputs (i1-UM, i2-UM) of a metastability circuit (UM) and inputs (i1-DF, i2-DF) of a phase detector (DF), which outputs (o-UM, o-DF) are connected to inputs (r-US′, i-US′) of a control circuit (US′), having output (o-US′) connected to control inputs (s-GPRS, s-GPRS′) of the adjustable speed ring oscillators (GPRS, GPRS′). The outputs (o-UM, o-DF) of the metastability circuit (UM) and the phase detector (DF) are being outputs (o-GL, o2-GL) of the random number generator (GL).