The invention provides a dynamic D flip-flop, and a data operation unit, a chip, a hash board and a computing device using the same. The dynamic D flip-flop comprises: an input terminal, an output terminal and at least one clock signal terminal; a latch unit for latching data of the input terminal and inversely transmitting the data under control of a clock signal; and an output driving unit for inverting and outputting the data received from the latch unit; wherein the latch unit outputs in high level, low level and high impedance states by means of a single element under control of a clock signal. Therefore, the invention can effectively reduce chip area, power consumption, and logic delay.

The invention provides a dynamic D flip-flop, and a data operation unit, a chip, a hash board and a computing device using the same. The dynamic D flip-flop comprises: an input terminal, an output terminal and at least one clock signal terminal; a first latch unit for transmitting data of the input terminal and latching the data under control of a clock signal; a second latch unit for latching data of the output terminal and inversely transmitting the data latched by the first latch unit under control of a clock signal; and an output driving unit for inverting and outputting the data received from the second latch unit; wherein the second latch unit outputs in high level, low level and high impedance states by means of a single element under control of a clock signal. Therefore, the invention can effectively reduce chip area, power consumption, and logic delay.

The invention provides a dynamic D flip-flop, and a data operation unit, a chip, a hash board and a computing device using the same. The dynamic D flip-flop comprises: an input terminal, an output terminal and at least one clock signal terminal; a first latch unit for transmitting data of the input terminal and latching the data under control of a clock signal; a second latch unit for latching data of the output terminal and inversely transmitting the data latched by the first latch unit under control of a clock signal; and an output driving unit for inverting and outputting the data received from the second latch unit; wherein the second latch unit outputs in high level, low level and high impedance states by means of a single element under control of a clock signal. Therefore, the invention can effectively reduce chip area, power consumption, and logic delay.

According to one aspect of embodiments, a driver circuit having an overcurrent protection function includes a control signal generating circuit that outputs a Pulse Width Modulation (PWM) control signal for controlling turning ON and OFF of the output transistor that supplies output current to a load; and a control circuit that generates a signal indicating an overcurrent state when a count value of an overcurrent detecting signal exceeds a predetermined number, which indicates that a value of an output current of the output transistor within the predetermined time interval exceeds a predetermined threshold value.

According to one aspect of embodiments, a driver circuit having an overcurrent protection function includes a control signal generating circuit that outputs a Pulse Width Modulation (PWM) control signal for controlling turning ON and OFF of the output transistor that supplies output current to a load; and a control circuit that generates a signal indicating an overcurrent state when a count value of an overcurrent detecting signal exceeds a predetermined number, which indicates that a value of an output current of the output transistor within the predetermined time interval exceeds a predetermined threshold value.

A clock generator includes a series of inverting stages; and at least one combinational logic stage. The series of inverting stages is tapped at two or more locations along the series of inverting stages to provide intermediary outputs. A combinational logic stage of the at least one combinational logic stage is coupled to receive two or more of the intermediary outputs and generate a clock signal. Multi-phase, multi-duty cycle, non-overlapping clock signals can be generated by the clock generator based on different combinations of intermediary outputs. The clock signals can be provided to a switching network.

A clock generator includes a series of inverting stages; and at least one combinational logic stage. The series of inverting stages is tapped at two or more locations along the series of inverting stages to provide intermediary outputs. A combinational logic stage of the at least one combinational logic stage is coupled to receive two or more of the intermediary outputs and generate a clock signal. Multi-phase, multi-duty cycle, non-overlapping clock signals can be generated by the clock generator based on different combinations of intermediary outputs. The clock signals can be provided to a switching network.

Embodiments of the disclosure provide a method, apparatus, and computer readable medium for optimizing memory card performance. The method includes: determining a plurality of different preset time intervals, the preset time intervals being determined beginning from clock-cycle starting points; sending test data to a memory card using each of the preset time intervals, respectively; reading from the memory card the test data corresponding to each of the preset time intervals; comparing the test data sent using each of the preset time intervals with the corresponding test data that is read; in response to the sent test data and the read test data being consistent, determining that the preset time interval is valid; determining at least one group of preset time intervals, each of the groups of preset time intervals containing a plurality of valid and successive preset time intervals; determining a group of preset time intervals containing a maximum number of preset time intervals as a target group; determining an average value of all the preset time intervals in the target group as a time interval for writing to the memory card.

Embodiments of the disclosure provide a method, apparatus, and computer readable medium for optimizing memory card performance. The method includes: determining a plurality of different preset time intervals, the preset time intervals being determined beginning from clock-cycle starting points; sending test data to a memory card using each of the preset time intervals, respectively; reading from the memory card the test data corresponding to each of the preset time intervals; comparing the test data sent using each of the preset time intervals with the corresponding test data that is read; in response to the sent test data and the read test data being consistent, determining that the preset time interval is valid; determining at least one group of preset time intervals, each of the groups of preset time intervals containing a plurality of valid and successive preset time intervals; determining a group of preset time intervals containing a maximum number of preset time intervals as a target group; determining an average value of all the preset time intervals in the target group as a time interval for writing to the memory card.

An image sensor may include an array of image sensor pixels. Pixel control circuitry may provide control signals to the array of image sensor pixels. The pixel control circuitry may include a plurality of driver units that each generate a control signal for a different set of image sensor pixels. The control signal generated by each of the driver units may be delayed relative to each other. A voltage-controlled delay line may provide delayed outputs to each of the driver units. Delay lock circuitry coupled to the voltage-controlled delay line may fix the delay exhibited across the delay line using corresponding global and local bias voltages provided to each of the inverters in the delay line.