A frequency selecting/switching circuit includes an input terminal, an output terminal, a two-way splitter circuit, a first phase-adjusting circuit, a second phase-adjusting circuit, a first switch, and a second switch. The two-way splitter circuit splits a signal inputted to the input terminal into first and second frequency components and outputs them to its first output end and second output end, respectively. The first output end and second output end of the two-way splitter circuit are connected to a first end of the first phase-adjusting circuit and a first end of the second phase-adjusting circuit, respectively. A second end of the first phase-adjusting circuit and a second end of the second phase-adjusting circuit are connected to the first switch and the second switch, respectively. Each switch switches an output of a signal inputted to its input end, to its output end between a conductive state and a non-conductive state.

Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further disclosed that determine, by a microcontroller, based on the phase measurements associated with the chiplet, a delay offset, and that delay, based on the delay offset, the propagation of the clock signal through the distribution tree of the chiplet using a delay unit associated with the chiplet.

In described examples, a quadrature phase shifter includes digitally programmable phase shifter networks for generating leading and lagging output signals in quadrature. The phase shifter networks include passive components for reactively inducing phase shifts, which need not consume active power. Output currents from the transistors coupled to the phase shifter networks are substantially in quadrature and can be made further accurate by adjusted by a weight function implemented using current steering elements. Example low-loss quadrature phase shifters described herein can be functionally integrated to provide low-power, low-noise up/down mixers, vector modulators and transceiver front-ends for millimeter wavelength (mmwave) communication systems.

Provided is a phase self-correction circuit, including a trigger signal operation module and a signal phase correction module. The trigger signal operation module and the signal phase correction module are both composed of a plurality of discrete components. The trigger signal operation module is configured to perform a logical operation on an input phase standard reference signal and actual transmission signal, to obtain a target trigger signal for triggering the signal phase correction module; and the signal phase correction module is configured to output, based on trigger modes of the target trigger signal and the actual transmission signal, a self-correction transmission signal with the same waveform as that of the phase standard reference signal, to realize phase self-correction on the actual transmission signal.

Apparatus and associated methods relate to a low-noise wideband active phase shifter. The low-noise wideband active phase shifter includes first and second transconductance cells, a fixed LC series network and a tunable LC series network configured to form an all-pass lattice network. The first and second transconductance cells, each include a transistor, a feedback network, and a transistor biasing network. The transistor has an input terminal and an output terminal. The negative feedback network electrically couples the input and output terminals of the transistor. The biasing network provides input and output biasing of the transistor. The fixed LC series network connects between the first and the second transconductance cells. The tunable LC series network connects between the first and the second transconductance cells.

A phase shift control circuit for a multi-channel system including a pulse control circuit and a current matching circuit is provided. The pulse control circuit includes first to third transistors, a front operational amplifier, comparers, a current mirror circuit, clock switch circuits and pulse generating circuits. The front operational amplifier has two input terminals connected to a voltage divider circuit and an output terminal of the first transistor respectively, and an output terminal connected to control terminals of all the transistors. One input terminal of the comparer is connected to an output terminal of the third transistor, and another input terminal of the comparer is connected to the output terminal of the first transistor or a reference voltage source. The pulse generators are connected to the comparers and the clock switch circuits respectively. The current mirror circuit is connected to the current matching circuit.

A method for electrically interconnecting two substrates, each having a corresponding set of preformed electrical contacts, the substrates comprising an electronic circuit, and the resulting module, is provided. A liquid curable adhesive is provided over the set of contacts of a first substrate, and the set of electrical contacts of the second substrate is aligned with the set of electrical contacts of the first substrate. The sets of electrical contacts of the first and second substrate are compressed to displace the liquid curable adhesive from the inter-contact region, and provide electrical communication between the respective sets of electrical contacts. The liquid curable adhesive is then cured to form a solid matrix which maintains a relative compression between the respective sets of electrical contacts. One embodiment of the module comprises a high-speed superconducting circuit which operates at cryogenic temperatures.

The techniques of this disclosure may digitally generate a driver signal with a period (or frequency) at a finer resolution than can be achieved by simply counting clock cycles of a system clock. The driver signal may be configured to trigger based on single output clock signal that may be phase-shifted relative to the master system clock. A clock phase shift circuit may increment the phase shift of the output clock signal to any fraction relative to the master system clock. A driver signal generated based on the phase-shifted output clock may achieve the high resolution in frequency desirable when controlling some pulse-width modulated circuits, such as an LLC converter.

A quadrature clock divider circuit includes a divide-by-2 circuit having at least one undivided clock input, and generates at least one quadrature clock component and at least one inverted quadrature clock component, each having a 50% duty cycle. A resync circuit has as inputs the at least one undivided clock input, and the uninverted and inverted quadrature clock components. The resync circuit uses the uninverted and inverted quadrature clock components as selectors to generate, from the undivided clock input signals, at least one second quadrature clock component on a first signal path and at least one second inverted quadrature clock component on a second signal path. The first and second signal paths have a first portion in common, and each of the at least one second quadrature clock component and the at least one second inverted quadrature clock component has a second duty cycle percentage other than 50%.

Duty cycle correction devices for static compensation of an active clock edge shift. A duty cycle correction circuit in the duty cycle correction device corrects a clock input signal, according to a first control signal. A programmable delay circuit or a modified duty cycle correction circuit in the duty cycle correction device compensates a shift of an active clock edge in a clock output signal of the duty cycle correction circuit, according to a second control signal. A mapping circuit in the duty cycle correction device generates the second control signal by mapping a digital value of the first control signal and a digital value of the second control signal.