Embodiments of the invention provide for a dynamic pulse generator which can combine both the sequential element and the pulse logic into one stage, thereby eliminating the wasted time resulting from a pulse generator' input-to-output propagation delay. The dynamic pulse generator can include a plurality of P-MOS an N-MOS transistors, a first delay element, and a second delay element.

A numerically-controlled oscillator (NCO) includes a phase accumulator (PA) which has a first input adapted to receive a phase increment, a second input adapted to receive a clock signal, and a third input adapted to receive a reset signal. The PA provides an instantaneous phase at an output. The NCO includes a dithered splitter which has an input coupled to receive the instantaneous phase. The dithered splitter dithers the instantaneous phase using a pseudo-random binary sequence (PRBS) and provides a dithered course phase and a dithered fine phase. The NCO includes a polynomial approximation unit which has a first input coupled to receive the dithered course phase and a second input coupled to receive the dithered fine phase. The polynomial approximation unit provides a sequence of numbers representing a discrete sinusoidal signal.

A numerically-controlled oscillator (NCO) includes a phase accumulator (PA) which has a first input adapted to receive a phase increment, a second input adapted to receive a clock signal, and a third input adapted to receive a reset signal. The PA provides an instantaneous phase at an output. The NCO includes a dithered splitter which has an input coupled to receive the instantaneous phase. The dithered splitter dithers the instantaneous phase using a pseudo-random binary sequence (PRBS) and provides a dithered course phase and a dithered fine phase. The NCO includes a polynomial approximation unit which has a first input coupled to receive the dithered course phase and a second input coupled to receive the dithered fine phase. The polynomial approximation unit provides a sequence of numbers representing a discrete sinusoidal signal.

A bi-directional buffer for applications using in an I2C or SMBUS or other bus systems. The bi-directional buffer has an input terminal to receive an input voltage signal and an output terminal for providing an output voltage signal, and the output voltage signal follows the input voltage signal. The output voltage signal is regulated to have a first bias voltage greater than the input voltage signal by a first operational amplifier, or to have a second bias voltage greater than the input voltage signal by a second operational amplifier, the second bias voltage is smaller than the first bias voltage.

A bi-directional buffer for applications using in an I2C or SMBUS or other bus systems. The bi-directional buffer has an input terminal to receive an input voltage signal and an output terminal for providing an output voltage signal, and the output voltage signal follows the input voltage signal. The output voltage signal is regulated to have a first bias voltage greater than the input voltage signal by a first operational amplifier, or to have a second bias voltage greater than the input voltage signal by a second operational amplifier, the second bias voltage is smaller than the first bias voltage.

A digitally controlled analog filter device. The digitally controlled analog filter device includes one or more digitally controlled analog signal amplifiers. The digitally controlled analog signal amplifiers are configured to have a gain of the digitally controlled analog signal amplifiers controlled by digital signals. The digitally controlled analog filter device further includes one or more analog time delay circuits coupled to signal input nodes of the digitally controlled analog signal amplifiers. The analog time delay circuits are configured to implement an analog signal delay. The digitally controlled analog filter device further includes a digital closed loop control circuit coupled to the digitally controlled analog signal amplifiers to digitally control the gain of the digitally controlled analog signal amplifiers.

A digitally controlled analog filter device. The digitally controlled analog filter device includes one or more digitally controlled analog signal amplifiers. The digitally controlled analog signal amplifiers are configured to have a gain of the digitally controlled analog signal amplifiers controlled by digital signals. The digitally controlled analog filter device further includes one or more analog time delay circuits coupled to signal input nodes of the digitally controlled analog signal amplifiers. The analog time delay circuits are configured to implement an analog signal delay. The digitally controlled analog filter device further includes a digital closed loop control circuit coupled to the digitally controlled analog signal amplifiers to digitally control the gain of the digitally controlled analog signal amplifiers.

A low-power clock generation circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts, a phase rotator circuit that outputs phase-adjusted clock signals, a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference, and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

A low-power clock generation circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts, a phase rotator circuit that outputs phase-adjusted clock signals, a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference, and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

An impedance measurement circuit and an operating method thereof are provided. The impedance measurement circuit includes a current source, a voltage controlled oscillator (VCO), an operation circuit, and a first delay circuit. The current source, electrically connected to a power rail, is able to sink a current from the power rail according to the delayed clock signal. The VCO is configured to generate an oscillation signal according to a power voltage on the power rail. The operation circuit is electrically connected to the VCO and is configured to receive a sampling clock signal and the oscillation signal, sense the power voltage to generate a sampled signal, and accumulate the sampled signal to generate a measurement result. The first delay circuit, electrically connected to the current source and the operation circuit, is able to receive the sampling clock signal and transmit the delayed clock signal to the current source.