An apparatus includes a current-to-voltage converter configured to convert first and second currents into first and second input voltages and provide the first and second input voltages to first and second nodes, respectively, and a current difference determination circuit configured to determine a difference between the first and second currents based on a difference between the first and second input voltages. A method includes converting first and second currents into first and second input voltages to output the first and second input voltages to first and second nodes, respectively, and determining a difference between the first and second currents based on a difference between the first and second input voltages.

An apparatus includes a current-to-voltage converter configured to convert first and second currents into first and second input voltages and provide the first and second input voltages to first and second nodes, respectively, and a current difference determination circuit configured to determine a difference between the first and second currents based on a difference between the first and second input voltages. A method includes converting first and second currents into first and second input voltages to output the first and second input voltages to first and second nodes, respectively, and determining a difference between the first and second currents based on a difference between the first and second input voltages.

Disclosed herein is a high-speed I/O circuit for die-to-die interconnect for suppressing an overshoot and an undershoot. A data reception circuit includes a reception circuit configured to convert a reception signal received from an interconnect into a digital signal, a first clipper circuit configured to suppress an overshoot of the reception signal based on current extraction, and a second clipper circuit configured to suppress an undershoot of the reception signal based on current supply.

Disclosed herein is a high-speed I/O circuit for die-to-die interconnect for suppressing an overshoot and an undershoot. A data reception circuit includes a reception circuit configured to convert a reception signal received from an interconnect into a digital signal, a first clipper circuit configured to suppress an overshoot of the reception signal based on current extraction, and a second clipper circuit configured to suppress an undershoot of the reception signal based on current supply.

A clock filter system and a clock filter switching method. The clock filter system includes a plurality of clock filters for respectively outputting a plurality of individual clock signals; a bypass circuit for outputting a bypass enable signal; a plurality of clock enable circuits for respectively outputting a plurality of enable signals; a feedback logic circuit for performing an inverse OR (NOR) operation on the bypass enable signal and the plurality of enable signals to generate a feedback signal; a plurality of clock control circuits for respectively generating and outputting a plurality of control signals according to the feedback signal and the plurality of enable signals to respectively control the plurality of individual clock signals to be turned on or turned off. When switching clock filters, a source individual clock signal and a target individual clock signal are controlled to be turned on at different times.

A clock filter system and a clock filter switching method. The clock filter system includes a plurality of clock filters for respectively outputting a plurality of individual clock signals; a bypass circuit for outputting a bypass enable signal; a plurality of clock enable circuits for respectively outputting a plurality of enable signals; a feedback logic circuit for performing an inverse OR (NOR) operation on the bypass enable signal and the plurality of enable signals to generate a feedback signal; a plurality of clock control circuits for respectively generating and outputting a plurality of control signals according to the feedback signal and the plurality of enable signals to respectively control the plurality of individual clock signals to be turned on or turned off. When switching clock filters, a source individual clock signal and a target individual clock signal are controlled to be turned on at different times.

An aspect relates to a filter or a first gyrator including a first set of cascaded inverters, and a first set of one or more passive devices coupled to the first set of cascaded inverters. Another aspect relates to a method including applying an input signal to an input of a first one of a set of cascaded inverters coupled to a set of one or more passive devices, and receiving an output signal from the set of cascaded inverters, the output signal being a filtered version of the input signal. Still another aspect relates to a transceiver including a filter with a first set of cascaded inverters, and a first set of one or more passive devices coupled to the first set of cascaded inverters; and a mixer coupled to the filter.

Mechanisms for detecting a voltage level on a data communication interface between a slave device and a host device are disclosed. Based on the detected voltage level, the slave device may respond to the host device on the data communication interface at the detected voltage level. The slave device may include a circuit configured to toggle between a first voltage level and a second voltage level to provide one of the first voltage level or the second voltage level corresponding to the detected voltage level on the data communication interface.

Mechanisms for detecting a voltage level on a data communication interface between a slave device and a host device are disclosed. Based on the detected voltage level, the slave device may respond to the host device on the data communication interface at the detected voltage level. The slave device may include a circuit configured to toggle between a first voltage level and a second voltage level to provide one of the first voltage level or the second voltage level corresponding to the detected voltage level on the data communication interface.

An example apparatus includes: first current source circuitry having a terminal; a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor coupled to the terminal of the first current source circuitry, the control terminal of the first transistor coupled to the terminal of the first frequency multiplier circuitry; second current source circuitry having a terminal; a second transistor having a first terminal and a second terminal, the first terminal of the second transistor coupled to the terminal of the second current source circuitry; an inductor having a first terminal and a second terminal; a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the first terminal of the inductor; and an amplifier having a terminal coupled to the second terminal of the first transistor, the second terminal of the second transistor.