A circuit for decoding a pulse width modulated (PWM) signal generates an output signal switching between a first and second logic values as a function of a duty-cycle of the PWM signal. Current generating circuitry receives the PWM signal and injects a current to and sinks a current from an intermediate node as a function of the values of the PWM signal. A capacitor coupled to the intermediate node is alternatively charged and discharged by the injected and sunk currents, respectively, to generate a voltage. A comparator circuit coupled to the intermediate node compares the generated voltage to a comparison voltage and drives the logic values of the output signal as a function of the comparison.

According to one aspect of the invention, there is provided a signal processing method, wherein a frame is generated in which at least one position of occurrence of a transition in a pulse value is determined from an input bitstream. According to another aspect of the invention, there is provided a signal processing method, wherein a frame including at least one pulse having a pulse width not less than a minimum pulse width is generated from an input bitstream.

A system includes a first controller configured to transmit a synchronization signal to a second controller. The second controller is configured to produce a PWM signal. The system also includes a counter configured to provide a count for the second controller, where the second controller is configured to initiate rising edges and falling edges of the PWM signal based on the count from the counter. The second controller is also configured to measure an error between a time when the synchronization signal is received at the second controller and an expected time of receipt for the synchronization signal. The second controller is also configured to adjust a period of the counter based at least in part on the error.

A duty timing detector includes a saw-tooth voltage generator that outputs a saw-tooth voltage in synchronization with a toggle signal repeatedly transitioning between a high level and a low level. A sample block obtains a level of the saw-tooth voltage in synchronization with the toggle signal and outputs the obtained level as a first sample voltage. A hold block stores the first sample voltage in synchronization with the toggle signal and outputs the stored first sample voltage as a second sample voltage. A voltage divider divides the second sample voltage to output a division voltage. A comparator compares the saw-tooth voltage and the division voltage to detect a target timing in each duty of the toggle signal.

Digital signal processing for mud pulse telemetry utilizes a variety of “On/Off” keying based modulation schemes, such as pulse width modulation (PWM) and pulse position modulation (PPM), to encode and/or decode information. A combination of PPM and PWM is disclosed that increases a bit rate while keeping a chip rate unchanged. The combination of PPM and PWM comprises determining a drilling condition and forming a message based on the drilling condition, forming a string of symbol values comprising the message, identifying a pulse width and a pulse start for the pulse based on a symbol value, providing a first pulse at a selected chip location, providing subsequent pulses to form the pulse width, and forming a quiet period at the end of the pulse width.

Digital signal processing for mud pulse telemetry utilizes a variety of “On/Off” keying based modulation schemes, such as pulse width modulation (PWM) and pulse position modulation (PPM), to encode and/or decode information. A combination of PPM and PWM is disclosed that increases a bit rate while keeping a chip rate unchanged. The combination of PPM and PWM comprises determining a drilling condition and forming a message based on the drilling condition, forming a string of symbol values comprising the message, identifying a pulse width and a pulse start for the pulse based on a symbol value, providing a first pulse at a selected chip location, providing subsequent pulses to form the pulse width, and forming a quiet period at the end of the pulse width.

A signal analysis method for analyzing a pulse modulated input signal is described. The signal analysis method includes: receiving the pulse modulated input signal, the input signal including a symbol sequence; recovering a clock signal from the input signal, the clock signal being associated with the input signal; sampling the input signal based on the clock signal, thereby obtaining a set of input signal samples, each of the input signal samples having a certain level being constant over time; determining at least two different levels of input signal samples being associated with different symbols of the symbol sequence; and determining at least one decision threshold based on the at least two different levels determined previously, the decision threshold being associated with a symbol transition of the symbol sequence. Further, a signal analysis apparatus is described.

A signal analysis method for analyzing a pulse modulated input signal is described. The signal analysis method includes: receiving the pulse modulated input signal, the input signal including a symbol sequence; recovering a clock signal from the input signal, the clock signal being associated with the input signal; sampling the input signal based on the clock signal, thereby obtaining a set of input signal samples, each of the input signal samples having a certain level being constant over time; determining at least two different levels of input signal samples being associated with different symbols of the symbol sequence; and determining at least one decision threshold based on the at least two different levels determined previously, the decision threshold being associated with a symbol transition of the symbol sequence. Further, a signal analysis apparatus is described.

A driving circuit, for providing a driving current to a light emitting diode, includes a PWM demodulator, a current source and a local clock generator. The PWM demodulator is configured to sample a PWM input signal in reference with a local clock signal and generate a brightness code according to a duty ratio of the PWM input signal. The current source is coupled with the PWM demodulator and the light emitting diode. The current source is configured to generate the driving current with a current amplitude according to the brightness code. The local clock generator is configured to generate the local clock signal according to a global clock signal during a first cycle period of successive cycle periods of the PWM input signal. The local clock generator suspends oscillation of the local clock signal during a second cycle period of the successive cycle periods of the PWM input signal.

Systems, methods, and circuits for determining a duty cycle of a periodic input signal are provided. A delay element is configured to delay the periodic input signal based on a digital control word. A digital circuit is configured to generate a first digital control word used to delay the periodic input signal a first amount of time corresponding to a period of the periodic input signal, generate a second digital control word used to delay the periodic input signal a second amount of time corresponding to a portion of the periodic input signal having a logic-level high value, and generate a third digital control word used to delay the periodic input signal a third amount of time corresponding to a portion of the periodic input signal having a logic-level low value. A controller is configured to determine the duty cycle based on the first, second, and third digital control words.