The present disclosure provides a serial PWM signal decoding circuit based on a capacitor charge-discharge structure, comprising: a timing logic generation circuit configured to receive, at an input end of the timing logic generation circuit, a PWM differential signal, and generate a timing logic signal; and at least two capacitor charge-discharge decoding modules, each of the at least two capacitor charge-discharge decoding modules has an input end connected to an output end of the timing logic generation circuit, and is configured to perform charging and discharging based on the timing logic signal. During a decoding process, a voltage at a charge-discharge capacitor of the capacitor charge-discharge decoding module before the charging and discharging is a common mode voltage VCM, and a voltage at a charge-discharge node after the end of the charging and discharging is a voltage V.sub.C, and the PWM signal is decoded by identify the PWM signal through determining a polarity of a voltage difference between the common mode voltage VCM and the voltage V.sub.C. The present disclosure further provides a method of decoding based on a capacitor charge-discharge structure. The present disclosure provides a simple structure and does not need synchronize code streams, thus avoiding the use of a complicated CDR and an oversampling structure, realizing the decoding of PWM signals at different rates, increasing the efficiency of signal transmission and lowering the power consumption.

The present disclosure provides a serial PWM signal decoding circuit based on a capacitor charge-discharge structure, comprising: a timing logic generation circuit configured to receive, at an input end of the timing logic generation circuit, a PWM differential signal, and generate a timing logic signal; and at least two capacitor charge-discharge decoding modules, each of the at least two capacitor charge-discharge decoding modules has an input end connected to an output end of the timing logic generation circuit, and is configured to perform charging and discharging based on the timing logic signal. During a decoding process, a voltage at a charge-discharge capacitor of the capacitor charge-discharge decoding module before the charging and discharging is a common mode voltage VCM, and a voltage at a charge-discharge node after the end of the charging and discharging is a voltage V.sub.C, and the PWM signal is decoded by identify the PWM signal through determining a polarity of a voltage difference between the common mode voltage VCM and the voltage V.sub.C. The present disclosure further provides a method of decoding based on a capacitor charge-discharge structure. The present disclosure provides a simple structure and does not need synchronize code streams, thus avoiding the use of a complicated CDR and an oversampling structure, realizing the decoding of PWM signals at different rates, increasing the efficiency of signal transmission and lowering the power consumption.

A duty timing detector includes a saw-tooth voltage generator that outputs a saw-tooth voltage in synchronization with a toggle signal repeatedly transitioning between a high level and a low level. A sample block obtains a level of the saw-tooth voltage in synchronization with the toggle signal and outputs the obtained level as a first sample voltage. A hold block stores the first sample voltage in synchronization with the toggle signal and outputs the stored first sample voltage as a second sample voltage. A voltage divider divides the second sample voltage to output a division voltage. A comparator compares the saw-tooth voltage and the division voltage to detect a target timing in each duty of the toggle signal.

A driving circuit, for providing a driving current to a light emitting diode, includes a PWM demodulator, a current source and a local clock generator. The PWM demodulator is configured to sample a PWM input signal in reference with a local clock signal and generate a brightness code according to a duty ratio of the PWM input signal. The current source is coupled with the PWM demodulator and the light emitting diode. The current source is configured to generate the driving current with a current amplitude according to the brightness code. The local clock generator is configured to generate the local clock signal according to a global clock signal during a first cycle period of successive cycle periods of the PWM input signal. The local clock generator suspends oscillation of the local clock signal during a second cycle period of the successive cycle periods of the PWM input signal.

A method for improving timing between solid state devices, e.g., in non-volatile memory device is described and includes generating timing signals from the data stream so that the data stream is free from synchronization bits. The PWM data stream is converted from CML to CMOS level. An even decoder decodes the even data signal. An odd decoder decodes the odd signal. The decoders rely on the respective signal, even or odd, to increase past a slower rising signal based on both the odd and even signals to change from a default low state to a high state. The clock signal is derived from edges of the data itself.

A method for improving timing between solid state devices, e.g., in non-volatile memory device is described and includes generating timing signals from the data stream so that the data stream is free from synchronization bits. The PWM data stream is converted from CML to CMOS level. An even decoder decodes the even data signal. An odd decoder decodes the odd signal. The decoders rely on the respective signal, even or odd, to increase past a slower rising signal based on both the odd and even signals to change from a default low state to a high state. The clock signal is derived from edges of the data itself.

An oscillator including two sequentially connected pulse generation circuits is disclosed. Each pulse generation circuit includes a charge/discharge circuit and a switch circuit and outputs a first or second signal depending on an input signal. The switch circuit controls the charge/discharge circuit so that the latter is charged when the input signal is at a first level and discharged when the input signal is at a second level higher than the first level. When the input signal is at the first level, the first signal is at the first level and the second signal is at the second level. When the input signal is at the second level, the first signal is at the second level and the second signal is at the first level. Upon completion of discharge of the charge/discharge circuit, the first signal changes to the first level and the second signal changes to the second level.

An oscillator including two sequentially connected pulse generation circuits is disclosed. Each pulse generation circuit includes a charge/discharge circuit and a switch circuit and outputs a first or second signal depending on an input signal. The switch circuit controls the charge/discharge circuit so that the latter is charged when the input signal is at a first level and discharged when the input signal is at a second level higher than the first level. When the input signal is at the first level, the first signal is at the first level and the second signal is at the second level. When the input signal is at the second level, the first signal is at the second level and the second signal is at the first level. Upon completion of discharge of the charge/discharge circuit, the first signal changes to the first level and the second signal changes to the second level.

A method for improving timing between solid state devices, e.g., in non-volatile memory device is described and includes generating timing signals from the data stream so that the data stream is free from synchronization bits. The PWM data stream is converted from CML to CMOS level. An even decoder decodes the even data signal. An odd decoder decodes the odd signal. The decoders rely on the respective signal, even or odd, to increase past a slower rising signal based on both the odd and even signals to change from a default low state to a high state. The clock signal is derived from edges of the data itself.

A method for improving timing between solid state devices, e.g., in non-volatile memory device is described and includes generating timing signals from the data stream so that the data stream is free from synchronization bits. The PWM data stream is converted from CML to CMOS level. An even decoder decodes the even data signal. An odd decoder decodes the odd signal. The decoders rely on the respective signal, even or odd, to increase past a slower rising signal based on both the odd and even signals to change from a default low state to a high state. The clock signal is derived from edges of the data itself.