A gate driver integrated circuit (IC) and a method of operating the same is provided. The gate driver IC is configured to drive a transistor between switching states in a power circuit, and includes a memory configured to store at least one measurement window parameter that defines a measurement interval; measurement circuitry configured to measure, over the measurement interval, a value corresponding to an operation of the power circuit, the measured value being proportional to an input capacitance of the transistor; processing circuitry configured to determine a correction factor based on the measured value, the correction factor being proportional to the input capacitance of the transistor; and a gate controller configured to control a gate current of the transistor based on the switching states and the correction factor.

A semi-controllable device driving method and apparatus and a hybrid device of the present disclosure belong to the electrical field, and are particularly a driving method, with no driving dead zone or with an extremely small driving dead zone, that is applicable to a semi-controllable device such as a thyristor; a semi-controllable driving apparatus, with no conduction dead zone or with an extremely small conduction dead zone, that is applicable to a driving loop of a semi-controllable device such as a thyristor; and a hybrid device with no conduction dead zone or with an extremely small conduction dead zone. In the semi-controllable device driving method, a voltage detection switch is used; an input end of the voltage detection switch is connected to two ends of a semi-controllable device that needs to be driven; the voltage detection switch is connected, in series, in a driving loop of the semi-controllable device; the voltage detection switch is turned on when a potential difference at the two ends of the semi-controllable device is not greater than an on-state voltage of the semi-controllable device; and the voltage detection switch is turned off after detecting that the semi-controllable device is turned on. The present disclosure has an advantage of no driving dead zone or an extremely small driving dead zone.

A first stacked RF switch, which operates in one of an ON mode and an OFF mode, and includes a group of RF switching circuits coupled in series between a first RF switch connection node and a second RF switch connection node, is disclosed. The group of RF switching circuits includes a first RF switching circuit, which includes a first switching transistor element coupled between a first source connection node and a first drain connection node, a first source/drain (S/D) bias resistive element coupled across the first switching transistor element, and a first S/D shorting circuit coupled across the first S/D bias resistive element. During the ON mode, the first switching transistor element is ON and the first S/D shorting circuit is ON. During a first interval immediately following a transition from the ON mode to the OFF mode, the first S/D shorting circuit is ON.

Apparatus and methods for biasing radio frequency (RF) switches to achieve fast switching are disclosed herein. In certain configurations, a switch bias circuit generates a switch control voltage for turning on or off a switch that handles RF signals. The switch bias circuit provides the switch control voltage to a control input of the switch by way of a resistor. Additionally, the switch bias circuit pulses the switch control voltage when turning on or off the switch to thereby shorten switching time. Thus, the switch can be turned on or off quickly, which allows the switch to be available for use soon after the state of the switch has been changed.

A gate-drive controller for a power semiconductor device includes a master control unit (MCU) and one or more comparators that compare the output signal of the power semiconductor device to a reference value generated by the MCU. The MCU, in response to a turn-off trigger signal, generates a first intermediate drive signal for the power semiconductor device and generates a second intermediate drive signal, different from the first drive signal, when a DSAT signal indicates that the power semiconductor device is experiencing de-saturation. The MCU generates a final drive signal for the power semiconductor when the output signal of the one or more comparators indicates that the output signal of the power semiconductor device has changed relative to the reference value. The controller may also include a timer that causes the drive signals to change in predetermined intervals when the one or more comparators do not indicate a change.

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C.sup.3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C.sup.3MOS logic with low power conventional CMOS logic. The combined C.sup.3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C.sup.3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C.sup.3MOS logic with low power conventional CMOS logic. The combined C.sup.3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Embodiments of the invention provide IGBT circuit modules with increased efficiencies. These efficiencies can be realized in a number of ways. In some embodiments, the gate resistance and/or voltage can be minimized. In some embodiments, the IGBT circuit module can be switched using an isolated receiver such as a fiber optic receiver. In some embodiments, a single driver can drive a single IGBT. And in some embodiments, a current bypass circuit can be included. Various other embodiments of the invention are disclosed.

Embodiments of the invention provide IGBT circuit modules with increased efficiencies. These efficiencies can be realized in a number of ways. In some embodiments, the gate resistance and/or voltage can be minimized. In some embodiments, the IGBT circuit module can be switched using an isolated receiver such as a fiber optic receiver. In some embodiments, a single driver can drive a single IGBT. And in some embodiments, a current bypass circuit can be included. Various other embodiments of the invention are disclosed.

A power source supply circuit includes: a plurality of power sources (11-1, 11-2) that generate power source voltages different from each other; a switch circuit (14) that switches and outputs the power source voltages generated in the plurality of power sources (11-1, 11-2); a voltage output terminal (16) that outputs outside the power source voltages output from the switch circuit (14); an RF choke circuit (15) provided between the switch circuit (14) and the voltage output terminal (16), the RF choke circuit (15) including a first capacitor; and a second capacitor (12-1, 12-2) provided between the plurality of power sources (11-1, 11-2) and the switch circuit (14), the second capacitor (12-1, 12-2) having a larger capacitance than the first capacitor.