A fully integrated GaN driver comprising a digital logic signal inverter, a level shifter circuit, a UVLO circuit, an output buffer stage, and (optionally) a FET to be driven, all integrated in a single package. The level shifter circuit converts a ground reference 0-5 V digital signal at the input to a 0-10 V digital signal at the output. The output drive circuitry includes a high side GaN FET that is inverted compared to the low side GaN FET. The inverted high side GaN FET allows switch operation, rather than a source follower topology, thus providing a digital voltage to control the main FET being driven by the circuit.

The present invention discloses a signal output apparatus. Each of two output circuits includes an inverter including an input terminal and an output terminal, and a resistor coupled between the output terminal and a differential output terminal. Each of MOS capacitors is coupled between the output terminals. Under a first operation mode, two current supplying circuits are disabled. The input terminals respectively receive a high and a low state input voltages and the output terminals generate a low and a high state output voltages. The capacitances become larger than a predetermined level. Under a second operation mode, one of the current supplying circuits is enabled to output a supplying current to the differential output terminal. The input terminals receive the high state input voltage. The output terminals generate the low state output voltage. The capacitances become not larger than the predetermined level.

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C.sup.3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C.sup.3MOS logic with low power conventional CMOS logic. The combined C.sup.3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C.sup.3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C.sup.3MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C.sup.3MOS logic with low power conventional CMOS logic. The combined C.sup.3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

An exemplary embodiment of the present invention discloses a voltage generation circuit of a display apparatus, including at least one resistor, a memory configured to store a resistance value set signal, a controller changing a resistance value of the resistor referring to the resistance value set stored in the memory, and a voltage generator connected to one end of the resistor and is configured to receive an input current corresponding to the resistance value of the resistor and generate a gate-on voltage corresponding to the input current.

An exemplary embodiment of the present invention discloses a voltage generation circuit of a display apparatus, including at least one resistor, a memory configured to store a resistance value set signal, a controller changing a resistance value of the resistor referring to the resistance value set stored in the memory, and a voltage generator connected to one end of the resistor and is configured to receive an input current corresponding to the resistance value of the resistor and generate a gate-on voltage corresponding to the input current.

The present invention provides a driving device and a control method. The driving device is configured to drive a power switch and includes a power supply, a first bridge arm coupled to the power supply, a second bridge arm coupled in parallel to the first bridge arm, and a resonant inductor. The first bridge arm includes a first switch and a second switch connected to a first midpoint, the second bridge arm comprises a first semiconductor element and a second semiconductor element connected to a second midpoint, and the resonant inductor is coupled between the first midpoint and the second midpoint. The control method includes turning on the first switch for a first period such that the power supply charges a gate electrode of the power switch; and in response to a decrease of a current of the resonant inductor to a first threshold value, turning on the first switch again for a second period such that a potential of the first midpoint is equal to a potential of the second midpoint.

A drive device driving a power converter that includes a switching element formed from a wide bandgap semiconductor, includes a PWM-signal output unit that generates a drive signal that drives the switching element with PWM; an on-speed reducing unit that, when the switching element is changed from off to on, reduces a change rate of the drive signal; and an off-speed improving unit that, when the switching element is changed from on to off, draws charge from the switching element at a high speed and with a charge drawing performance higher than that at a time when the switching element is changed from off to on.

An analog switch includes an input terminal, an output terminal, a common gate, and a common source. The switch includes a current source which has a first input coupled to a first voltage supply, a control input coupled to receive a gate boost signal, and an output coupled to the common gate. The current source supplies a boost gate current to the common gate during a boost period and supplies a reduced gate current during a second period different than the boost period. The switch includes a clamp circuit which has a first terminal coupled to the common gate, a second terminal coupled to the common source, and a third terminal. The switch includes a Vgs detection circuit which provides the gate boost signal responsive to a conduction of current through the clamp circuit.

An analog switch includes an input terminal, an output terminal, a common gate, and a common source. The switch includes a current source which has a first input coupled to a first voltage supply, a control input coupled to receive a gate boost signal, and an output coupled to the common gate. The current source supplies a boost gate current to the common gate during a boost period and supplies a reduced gate current during a second period different than the boost period. The switch includes a clamp circuit which has a first terminal coupled to the common gate, a second terminal coupled to the common source, and a third terminal. The switch includes a Vgs detection circuit which provides the gate boost signal responsive to a conduction of current through the clamp circuit.