We describe a system for controlling very large numbers of power semiconductor switching devices (132) to switch in synchronization. The devices are high power devices, for example carrying hundreds of amps and/or voltages of the order of kilovolts. In outline the system comprises a coordinating control system (110, 120), which communicates with a plurality of switching device controllers (130) to control the devices into a plurality of states including a fully-off state, a saturated-on state, and at least one intermediate state between the fully-off and saturated-on states, synchronizing the devices in the at least one intermediate state during switching.

We describe a system for controlling very large numbers of power semiconductor switching devices (132) to switch in synchronization. The devices are high power devices, for example carrying hundreds of amps and/or voltages of the order of kilovolts. In outline the system comprises a coordinating control system (110, 120), which communicates with a plurality of switching device controllers (130) to control the devices into a plurality of states including a fully-off state, a saturated-on state, and at least one intermediate state between the fully-off and saturated-on states, synchronizing the devices in the at least one intermediate state during switching.

B-TRAN bipolar power transistor devices and methods, using a drift region which is much thinner than previously proposed double-base bipolar transistors of comparable voltage. This is implemented in a high-bandgap semiconductor material (preferably silicon carbide). Very high breakdown voltage, and fast turn-off, are achieved with very small on-resistance.

B-TRAN bipolar power transistor devices and methods, using a drift region which is much thinner than previously proposed double-base bipolar transistors of comparable voltage. This is implemented in a high-bandgap semiconductor material (preferably silicon carbide). Very high breakdown voltage, and fast turn-off, are achieved with very small on-resistance.

The invention relates to a method (100) and a control device (SG) for operating power semiconductor switches (LH1 . . . LHn) connected in parallel, having the following steps: determining a nominal value for a total gate series resistor (GGVL . . . GGVn) of at least one power semiconductor switch (LH1 . . . LHn); providing the total gate series resistor (GGV1 . . . GGVn) for the at least one power semiconductor switch (LH1 . . . LHn) depending on the relevant nominal value, and operating the at least one power semiconductor switch (LH1 . . . LHn) with the associated total gate series resistor (GGV1 . . . GGVn).

The invention relates to a method (100) and a control device (SG) for operating power semiconductor switches (LH1 . . . LHn) connected in parallel, having the following steps: determining a nominal value for a total gate series resistor (GGVL . . . GGVn) of at least one power semiconductor switch (LH1 . . . LHn); providing the total gate series resistor (GGV1 . . . GGVn) for the at least one power semiconductor switch (LH1 . . . LHn) depending on the relevant nominal value, and operating the at least one power semiconductor switch (LH1 . . . LHn) with the associated total gate series resistor (GGV1 . . . GGVn).

The disclosure relates to a method and a control device for controlling at power semiconductor switches connected in parallel for switching a total current. The semiconductor switches each have a gate terminal. An input terminal for feeding the total current, an output terminal for discharging the total current, and a joint control terminal for receiving a joint control signal that has the state ‘disconnect’ or ‘connect’ are provided. The power semiconductor switches are each connected between to the input terminal and the output terminal. At least one ascertainment unit is designed to receive the joint control signal, ascertain individual control signals in accordance with the joint control signal to control the individual power semiconductor switches, and output the individual control signals to the gate terminals of the power semiconductor switches. The individual control signals each have the state ‘disconnect’ or ‘connect’ and differ at least temporarily.

This electric energy converter for converting a first energy into a second energy comprises two first terminals for the first energy, at least one second terminal for the second electric energy, P switching arms, each including two switching half-arms connected in series between the two first terminals and connected to one another at a midpoint that is connected to a respective second terminal. Each half-arm including N switching half-branches connected in parallel, N≧2, each switching half-branch including a switch.

This converter further comprises 2×P control modules, each control module being configured to control the switches of a respective half-arm, each control module including an output terminal for each respective switch, each output terminal being configured to deliver a control signal for said respective switch.

A control circuit for an electronic switch includes a first power switch receiving a common input signal and a first voltage input and a second power switch receiving the common input signal and a second voltage input. The first and second power switches switchably connect the first voltage input and the second voltage input, respectively, to a common output in response to the common input signal. The second voltage input is opposite in polarity to the first voltage input, and the first power switch and the second power switch are configured to asynchronously connect the first voltage input and the second voltage input, respectively, to the common output in response to the common input signal, the electronic switch being switched according to the first voltage input or the second voltage input being connected to the common output.

Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.