A differential signal input buffer is disclosed. The differential signal input buffer may receive a differential signal that includes a first signal and a second signal and may be divided into a first section and a second section and. The first section may buffer and/or amplify the first signal based on a first level-shifted second signal. The second section may buffer and/or amplify the second signal based on a first level-shifted first signal. In some implementations, the first section may buffer and/or amplify the first signal based on a second level-shifted second signal. Further, in some implementations, the second section may buffer and/or amplify the second signal based on a second level-shifted first signal.

A power switch fault detector detects faults in the current paths of power switches. A first operational amplifier detects a drain-source voltage of a first set of parallel connected field-effect transistors in a current path. A second operational amplifier detects a drain-source voltage of a second set of parallel connected field-effect transistors in the current path. A hardware or software processor is configured to compare a difference in magnitude of the drain-source voltages to a threshold voltage to determine whether a field-effect transistor of one of the first set or second set is compromised. The current path is isolated and one of the first set or second set of field-effect transistors is deactivated to determine whether a field-effect transistor of the first set or second set is stuck-open or shorted.

Current sharing among bidirectional double-base bipolar junction transistors. One example is a method comprising: conducting current through a first bidirectional double-base bipolar junction transistor (first B-TRAN); conducting current through a second B-TRAN the second B-TRAN coupled in parallel with the first B-TRAN; measuring a value indicative of conduction of the first B-TRAN, and measuring a value indicative of conduction of the second B-TRAN; and adjusting a current flow through the first B-TRAN, the adjusting responsive to the value indicative of conduction of the first B-TRAN being different than the value indicative of conduction of the second B-TRAN.

Apparatus and associated methods relate to an input buffer having a source follower connected in series with a push-pull driver to generate a shield reference node that provides conductive traces extending from the shield reference node and disposed between gate traces of the input buffer and a corresponding nearest reference potential node. In an illustrative example, the push-pull driver and the source follower may be capacitively coupled, via the gate traces, to receive an input signal from an input node. In some examples, the shield reference node may also include conductive traces disposed between the input node and/or the gate traces and a corresponding nearest reference potential node such that parts of parasitic capacitances in the input buffer may be shielded. Accordingly, the bandwidth of the input buffer may be advantageously improved. The high frequency return loss (S.sub.11) may also be improved accordingly.

A switching device 1 includes a SiC semiconductor chip 11 which has a gate pad 14, a source pad 13 and a drain pad 12 and in which on-off control is performed between the source and the drain by applying a drive voltage between the gate and the source in a state where a potential difference is applied between the source and the drain, a sense source terminal 4 electrically connected to the source pad 13 for applying the drive voltage, and an external resistance (source wire 16) that is interposed in a current path between the sense source terminal 4 and the source pad 13, is separated from sense source terminal 4, and has a predetermined size.

A switching device 1 includes a SiC semiconductor chip 11 which has a gate pad 14, a source pad 13 and a drain pad 12 and in which on-off control is performed between the source and the drain by applying a drive voltage between the gate and the source in a state where a potential difference is applied between the source and the drain, a sense source terminal 4 electrically connected to the source pad 13 for applying the drive voltage, and an external resistance (source wire 16) that is interposed in a current path between the sense source terminal 4 and the source pad 13, is separated from sense source terminal 4, and has a predetermined size.

An improved gate driver using a microcontroller (uC), a voltage selector (VS), an adjustable voltage regulator (AVR), and an auxiliary current sinking circuit (ACSC) to actively provide selectable drive signals either higher, lower or equal to the basic on voltage and off voltage drive signals for a selected semiconductor device thereby providing an active voltage-mode gate driver for actively speeding up or slowing both the on time and off time transitions of a semiconductor.

A current flow control device includes a plurality of semiconductor switches disposed between a power source and a load and that are connected in parallel with each other, and the current flow control device being configured to control the flow of current between the power source and the load by turning on and off the semiconductor switches. The plurality of semiconductor switches include a first and a second semiconductor switch. The current flow control device includes a driving circuit configured to apply, to the first semiconductor switch, a voltage that is higher than a voltage output from the power source, to turn on the first semiconductor switch, a switch control unit configured to turn on the second semiconductor switch, and a resistor that is connected in series with a terminal on the power source side of the second semiconductor switch, the resistor lowering a voltage applied to the terminal.

A device includes a laterally diffused MOSFET, which in turn includes n-type source and drain regions in a p-type semiconductor substrate. A gate electrode is located over the semiconductor substrate between the source region and the drain region. An isolation region is laterally spaced apart from the source region, and is bounded by an n-type buried layer and an n-type well region that reaches from a surface of the substrate to the buried layer. A p-type doped region and an n-type doped region are disposed within the isolation region, the p-type doped region and the n-type doped region forming a diode. A first conductive path connects the n-type doped region to the source region, and a second conductive path connects the p-type doped region to the gate electrode.

An apparatus is described having: a baseplate; an AC busbar mounted on the baseplate; a DC busbar having an upper DC busbar, a lower DC busbar and an insulating material therebetween, wherein the DC busbar is mounted such that the lower DC busbar is mounted to the baseplate and wherein the upper DC busbar has one or more openings through which the lower DC busbar is exposed; a first group of switching components mounted on the AC busbar, wherein the first group of switching components are connected to the upper DC busbar using first electrical connection means; and a second group of switching components mounted on the lower DC busbar, wherein at least one of the switching components of said second group of switching components is mounted within one of said openings, wherein the second group of switching components are to the AC busbar using second electrical connection means.