A switch assembly configured to determine when input received from a switch is caused by proper actuation of the switch and should be accepted, or is caused instead by a fault in the switch or in the intervening circuitry and should be ignored and/or reported. The switch assembly optionally includes a logic circuit that is electrically connected to the switch. The logic circuit may provide power to the switch, for example, as a time varying signal, which may then be presented to the logic circuit as input when the switch is properly actuated. The logic circuit may then compare the input from the switch with the signal sent to the switch to determine if a fault is present, or if the switch is operating properly.

A switch assembly configured to determine when input received from a switch is caused by proper actuation of the switch and should be accepted, or is caused instead by a fault in the switch or in the intervening circuitry and should be ignored and/or reported. The switch assembly optionally includes a logic circuit that is electrically connected to the switch. The logic circuit may provide power to the switch, for example, as a time varying signal, which may then be presented to the logic circuit as input when the switch is properly actuated. The logic circuit may then compare the input from the switch with the signal sent to the switch to determine if a fault is present, or if the switch is operating properly.

One example of the present disclosure is an integrated circuit (IC). The IC includes an inverter with an input and an output, a clock transmission gate coupled to the output of the inverter; and a plurality of storage cells. The clock transmission gate is coupled to each of the plurality of storage cells, wherein each of the plurality of storage cells comprises a plurality of nodes arranged based on a minimum spacing.

One example of the present disclosure is an integrated circuit (IC). The IC includes an inverter with an input and an output, a clock transmission gate coupled to the output of the inverter; and a plurality of storage cells. The clock transmission gate is coupled to each of the plurality of storage cells, wherein each of the plurality of storage cells comprises a plurality of nodes arranged based on a minimum spacing.

An interface circuit includes: a buffer circuit configured to receive an input signal and to generate an output signal having a delay time, the delay time being determined based on a current level of a bias current and a voltage level of a power supply voltage; and a bias generation circuit configured to vary a voltage level of a bias control voltage so that the delay time is constant by compensating for a change in the voltage level of the power supply voltage, the bias generation circuit being further configured to provide the bias control voltage to the buffer circuit.

A power domain change circuit includes an input circuit and an output circuit. The input circuit is suitable for operating in a first power domain and generating first and second intermediate processing signals. The output circuit is suitable for operating in a second power domain and generating a final output signal by averaging and combining transition jitter components of the first and second intermediate processing signals.

A power domain change circuit includes an input circuit and an output circuit. The input circuit is suitable for operating in a first power domain and generating first and second intermediate processing signals. The output circuit is suitable for operating in a second power domain and generating a final output signal by averaging and combining transition jitter components of the first and second intermediate processing signals.

An input/output (I/O) circuit may be provided. The I/O circuit may include an input control circuit and an output control circuit. The input control circuit may be configured to apply a stress to a transmission path based on an input signal while in a test mode and buffer the input signal using a drivability changed by the stress applied to the transmission path to generate first and second transmission signals while in a normal mode after the test mode. The output control circuit may be configured to drive and output an output signal according to the first and second transmission signals based on a test mode signal.

Switch circuitry including an input terminal (1), said input terminal connected to the base of a first transistor (Q1) via a first resistor (R3), said first transistor being an NPN Bipolar Gate Transistor (Q1), said circuitry further comprising a second resistor (R5) connected between the base of said first transistor (Q1) and ground, and including an output line or terminal (3) connected to the collector of said first transistor (Q1), and wherein the emitter of said first transistor (Q1) is connected to ground (earth), said circuitry further including a second transistor (Q2), said second transistor being a PNP Bipolar Gate Transistor, wherein the collector of said second transistor (Q2) is connected via a third resistor (R8) to the base of said first transistor (Q1), and the emitter of said second transistor (Q2) is connected to said input terminal (1), and wherein the emitter of said second transistor (Q2) is additionally connected to the base of said second transistor (Q2) via a fourth resistor (R11); and the base of said second transistor (Q2) being additionally connected to the output terminal (3) via a fifth resistor (R10) and a diode (D1).

A memory system includes a memory array comprising a plurality of memory cells. Each of the memory cells includes a first programming transistor, a second programming transistor, a first reading transistor coupled to the first programming transistor in series, and a second reading transistor coupled to the second programming transistor in series. The memory system includes an authentication circuit operatively coupled to the memory array. The authentication circuit is configured to generate a Physically Unclonable Function (PUF) signature based on respective logic states of the plurality of memory cells. The logic state of each of the plurality of memory cells is determined based on a preceding breakdown of either the corresponding first programming transistor or second programming transistor.