An input/output module includes a multiplexing circuit, which is responsive to a plurality of I/O signals and configured to output a selected one of the plurality of I/O signals according to a value of a common input signal received at a control terminal thereof. A level shifting circuit is provided, which is configured to convert a voltage level of the selected one of the plurality of I/O signals and a voltage level of the common input signal. At least two functional blocks are provided, which are each configured to receive the selected one of the plurality of I/O signals having the converted voltage level, yet operate in a mutually exclusive manner according to a value of the common input signal having the converted voltage level.

An output driving circuit includes: a plurality of bias voltage generating circuits configured to generate a plurality of bias voltages; a switching control circuit; and an output voltage generating circuit. The switching control circuit is configured to selectively connect one bias voltage generating circuit of the plurality of bias voltage generating circuits to the output voltage generating circuit based on an output voltage. The output voltage generating circuit is configured to transmit and receive a parasitic current generated due to transition of the output voltage to and from the one bias voltage generating circuit selectively connected to the output voltage generating circuit through the switching control circuit.

A device for synchronous serial data transmission over a differential data channel and a differential clock channel includes an interface controller having a clock generator, data controller, clock transmitter block and data receiver block. The clock generator generates a transmit clock signal which, during a data transmission cycle, includes a clock pulse train having a period. The clock generator is suitably configured such that, for data transmission cycles in a dynamic operating state in which a maximum occurring differential voltage of a differential clock signal is lower than a maximum differential voltage of the clock transmitter block, the clock generator sets a duration of a first clock phase of a first clock period of the clock pulse train to be longer than a first clock phase of following clock periods and shorter than a time duration required to reach the maximum differential voltage.

A daisy-chain battery cells system having a plurality of differential communication interfaces {F(i), i=1, . . . , N} respectively coupled to a plurality of voltage measuring modules {S(i), i=1, . . . , N} for a plurality of battery cells {C(i), i=1, . . . , N}. For each i=1, . . . , N−1, a first high side differential pin pair (CLU(i)+, CLU(i)−) of the i.sup.th differential communication interface F(i) is coupled to a first low side differential pin pair (CLL(i+1)+, CLL(i+1)−) of the (i+1).sup.th differential communication interface F(i+1), and a second high side differential pin pair (DAU(i)+, DAU(i)−) of the i.sup.th differential communication interface F(i) is coupled to a second low side differential pin pair (DAL(i+1)+, DAL(i+1)−) of the (i+1).sup.th differential communication interface F(i+1). A low side interface FL(1) of the first differential communication interface F(1) is coupled to a controller. A high side interface FU(N) of the N.sup.th differential communication interface F(N) may receive a preset data/signal.

A device for buffering a reference signal comprises a regulator circuit configured to generate at least two replicas of the reference signal as regulated output signals. The device further comprises a receiving circuit configured to receive the regulated output signals in a switchable manner. In this context, the regulated output signals are configured to have different performance characteristics.

A charging cable has a current sensor, a charging state indicator and logic circuitry to operate the indicator based on detected levels of current flow to a chargeable device. If the sensor detects current below a low threshold, the logic circuitry operates the indicator to indicate that the cable is not connected to any chargeable device. If the sensor detects current above a higher threshold, the logic circuitry operates the indicator to provide a perceptible output indicating that the cable is connected to the chargeable device and the current is charging the battery. If the sensor detects current at or above the low threshold but below the high threshold, the logic circuitry operates the indicator to provide a perceptible output indicating that the cable is connected to a chargeable device but is not charging the battery of the device, e.g., when the battery is, or is nearly, fully charged.

A charging cable has a current sensor, a charging state indicator and logic circuitry to operate the indicator based on detected levels of current flow to a chargeable device. If the sensor detects current below a low threshold, the logic circuitry operates the indicator to indicate that the cable is not connected to any chargeable device. If the sensor detects current above a higher threshold, the logic circuitry operates the indicator to provide a perceptible output indicating that the cable is connected to the chargeable device and the current is charging the battery. If the sensor detects current at or above the low threshold but below the high threshold, the logic circuitry operates the indicator to provide a perceptible output indicating that the cable is connected to a chargeable device but is not charging the battery of the device, e.g., when the battery is, or is nearly, fully charged.

A level converter and circuit arrangement comprising such level converters. The level converter comprises a transistor, an impedance converter, an input voltage connection, an output voltage connection, and a power supply connection. The input voltage connection is connected to a gate terminal of the transistor. The output voltage connection is connected to a source terminal of the transistor and to the power supply connection. A first input terminal of the impedance converter is connected to the source connection or to the gate terminal of the transistor. An output terminal of the impedance converter is connected to the drain terminal of the transistor. The power supply connection is equipped to receive a current from a constant current source. The impedance converter is equipped to keep a source-drain voltage of the transistor at a predefined value using a reference voltage.

An integrated circuit device having separate dies for programmable logic fabric and circuitry to operate the programmable logic fabric are provided. A first integrated circuit die may include field programmable gate array fabric. A second integrated circuit die may be coupled to the first integrated circuit die. The second integrated circuit die may include fabric support circuitry that operates the field programmable gate array fabric of the first integrated circuit die.

A hybrid automatic level control (ALC) system for controlling analog outputs. Within the ALC, a feedback loop passes from an analog circuit to a digital circuit and may provide the level of the analog output to the digital circuit. The digital circuit may use lookup tables to model the responses of analog devices but without associated errors and complications of the analog domain. Some examples of the modeled response include linear frequency responses of analog diodes and frequency responses of analog filters. Based on the received feedback and using the lookup tables modeling the responses, the digital circuit may drive a digital-to-analog converter interfacing the analog circuit to control the level of the analog output.