Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.

A semiconductor device and a method for controlling body bias thereof capable of properly controlling body bias of a transistor even in a case where process variation occurs are provided. Operation speeds of ring oscillators ROSCn and ROSCp respectively change due to an influence of process variation at an NMOS transistor MN side and a PMOS transistor MP side. Speed/bias data represent a correspondence relationship between the operation speeds of the ring oscillators ROSCn and ROSCp and set values V1n and V1p of body biases VBN and VBP. A body bias controller receives speed values Sn and Sp measured for the ring oscillators ROSCn and ROSCp to which the body biases VBN and VBP based on default values are respectively applied, and obtains the set values V1n and V1p on the basis of the speed/bias data.

A transistor device is disclosed. The transistor device includes: a semiconductor body (100); a drift region (11) in the semiconductor body (100); a plurality of transistor cells (10); and a gate node (G) and a source node (S), wherein each of the plurality of transistor cells (10) includes: a first trench electrode (21) insulated from the semiconductor body (100) by a first dielectric layer (22); a second trench electrode (23) insulated from the semiconductor body (100) by a second dielectric layer (24); a source region (13) and a body region (14) in a first mesa region (111) between the first trench electrode (21) and the second trench electrode (23); and a compensation region (12), wherein the compensation region (12) adjoins the body region (14), the first dielectric (22), the second dielectric (24), and forms a pn-junction with the drift region (11), and wherein from the first trench electrode (21) and the second trench electrode (23) at least the first trench electrode (21) is connected to the gate node (G).

This application relates to a charging protection circuit. The charging protection circuit implements overcurrent protection by using a four-terminal NMOS switching transistor. In the solution provided in this application, floating management is performed on a Sub port of the four-terminal NMOS switching transistor. Specifically, when the four-terminal NMOS switching transistor is turned on, potential of the Sub port is pulled up, to avoid an excessively large internal resistance of the four-terminal NMOS switching transistor caused by an excessively large voltage between the Sub port and a drain of the four-terminal NMOS switching transistor. In addition, this application further provides a charging circuit and an electronic device.

Field effect transistors in an electronic switching device are provided with electrostatic discharge (ESD) protection elements electrically coupled to a first current terminal of each transistor (e.g., a source of each transistor or a drain of each transistor), allowing the electronic switching device to withstand ESD-induced currents without damage to the switching device.

A bidirectional GaN FET with a single gate formed by integrating a single-gate bidirectional GaN FET in parallel with a bidirectional device formed of two back-to-back GaN FETs with a common source. The single-gate bidirectional GaN FET occupies most of the integrated circuit die, such that the integrated device has a low channel resistance, while also capturing the advantages of a back-to-back bidirectional GaN FET device.

A switching driver circuit may have an output stage having an output switch connected between a switching voltage node and an output node. A switch network may control a switching voltage at the switching voltage node so that in one mode the switching voltage node is coupled to a positive voltage and in another mode the switching voltage node is coupled to ground voltage via a first switching path of the switch network. The circuit may also include an n-well switching block operable to, when the first switching voltage node is coupled to a positive voltage, connect the n-well of the first output switch to the switching voltage node, and, when the first switching voltage node is coupled to the ground voltage, connect the n-well of the first output switch to a first ground which is separate to the first switching voltage node and independent of the first switching path.

An apparatus for reducing switching time of RF FET switching devices is described. A FET switch stack includes a stacked arrangement of FET switches and a plurality of gate feed arrangements, each coupled at a different height of the stacked arrangement. A circuital arrangement with a combination of a series RF FET switch and a shunt RF FET switch, each having a stack of FET switches, is also described. The shunt switch has one or more shunt gate feed arrangements with a number of bypass switches that is less than the number of FET switches in the shunt stack.

Methods and devices to address the undesired DC voltage distribution across switch stacks in OFF state are disclosed. The disclosed devices include charge control elements that sample the RF signal to generate superimposed voltages at specific points of the switch stack biasing circuit. The provided voltages help reducing the drooping voltages on drain/source/body terminals of the transistors within the stack by supplying the current drawn by drain/source terminals of the stacked transistors and/or by sinking the body leakage current exiting the body terminals of such transistors. Methods and techniques teaching how to provide proper tapping points in the biasing circuit to sample the RF signal are also disclosed.

An analogue switch arrangement includes an analogue switch including a first and second transistor in parallel between an input terminal and an output terminal and an input transistor arrangement including a first control transistor, a second control transistor, a first voltage control transistor and a second voltage control transistor. The gate terminals of both the first and second transistors are configured to receive a first and second control signal for controlling the analogue switch between an on-state and an off-state. The gate terminals of both the first and second voltage control transistors are configured to receive a voltage based on the voltage at the output terminal to provide for control of the voltage applied at the input terminal based on the voltage at the output terminal when the analogue switch is in the off-state.