In accordance with embodiments of the present disclosure, systems and methods may include an input configured to indicate a switching node voltage of a switching node of a power converter comprising a first switch device coupled at its non-gate terminals between a ground voltage and the switching node and a second switch device coupled at its non-gate terminals between an output supply node and the switching node. The systems and methods may also include a predriver circuit coupled to the input and a gate terminal of the first switch device, the predriver circuit configured to drive an input voltage signal to the gate terminal of the first switch device and configured to select an effective impedance of the gate terminal of the first switch device based on the input.

An example of a totem-pole bridgeless power factor correction circuit includes a first drive circuit, a rectifier bridge, an inductor, and a current detection circuit. The rectifier bridge includes a first metal oxide semiconductor (MOS) transistor and a first resistor that are located in a first bridge arm. The first drive circuit is configured to drive, based on a first PWM signal when a voltage of a second output port of an alternating current power supply is a positive voltage, a first port and a second port of the first MOS transistor to turn on the first MOS transistor to enable the alternating current power supply to charge the inductor by using the first MOS transistor. The first resistor is configured to convert a current flowing through the first MOS transistor into a corresponding first voltage signal

The invention relates to a circuit arrangement (1), in particular for controlling an electric machine, comprising at least one high-voltage semiconductor bridge circuit (2) that includes a low-side semiconductor switch (4) and a high-side semiconductor switch (3). A high-side gate driver (5) is assigned to the high-side semiconductor switch (3), and a low-side gate driver (6) is assigned to the low-side semiconductor switch (4). According to the invention, a high-side flyback converter (8) is connected upstream of the high-side gate driver, and a low-side flyback converter (9) is connected upstream of the low-side gate driver (6), at least one of the flyback converters (7, 8, 9) being designed as a high-voltage flyback converter.

An apparatus and method for testing gallium nitride field effect transistors (GaN FETs) are disclosed herein. In some embodiments, the apparatus includes: a high side GaN FET, a low side GaN FET, a high side driver coupled to a gate of the high side GaN FET, a low side driver coupled to a gate of the low side GaN FET, and a driver circuit coupled to the high side and low side drivers and configured to generate drive signals capable of driving the high and low side GaN FETs, wherein the high and low side GaN FETs and transistors, within the high and low side drivers and the driver circuit, are patterned on a same semiconductor device layer during a front-end-of-line (FEOL) process.

A bootstrapping gate driver circuit in which the size of the bootstrap capacitors is reduced. The gate-to-source voltage of the high side (pull-up) FET is pre-driven to an initial voltage (pre-driven voltage) before the bootstrap capacitor releases charge to charge up the gate-to-source voltage of the high side FET. This pre-driven voltage is applied through a pre-driven FET that allows current flow from the supply voltage to charge the gate of the high side FET to the pre-driven voltage. The pre-driven FET is turned on by a turn-on signal that occurs before the bootstrap capacitor releases charge. The pre-driven period (and hence, the pre-driven voltage) is determined from the time that the pre-driven FET begins to turn on, to the time that the bootstrap capacitor starts to release charge.

A semiconductor device includes: a semiconductor base body; a first region of a first conductivity type selectively provided in an upper part of the semiconductor base body; a second region of a second conductivity type provided in contact with the first region in the upper part of the semiconductor base body; a third region of the second conductivity type provided away from the second region in the upper part of the semiconductor base body; a fourth region of the second conductivity type provided between the second region and the third region in the upper part of the semiconductor base body; a first isolation region provided between the second region and the fourth region; and a second isolation region provided between the third region and the fourth region.

A semiconductor device according to related art has a problem that a clamp voltage that clamps an output voltage cannot adaptively vary in accordance with a power supply voltage, and it is thus not possible to reduce heating of a semiconductor chip to a sufficiently low level. According to one embodiment, a semiconductor device includes a drive circuit (10) that controls on and off of an output transistor (13) and an overvoltage protection circuit (12) that controls a conductive state of the output transistor (13) when an output voltage Vout reaches a clamp voltage, and the overvoltage protection circuit (12) has a circuit structure that sets the clamp voltage to vary in proportion to a power supply voltage VDD.

Hybrid power switching stages and driver circuits are disclosed. An example semiconductor power switching device comprises a high-side switch and a low-side switch connected in a half-bridge configuration, wherein the high-side switch comprises a GaN power transistor and the low-side switch comprises a Si MOSFET. The Si—GaN hybrid switching stage provides enhanced performance, e.g. reduced switching losses, in a cost-effective solution which takes advantage of characteristics of power switching devices comprising both GaN power transistors and Si MOSFETs. Also disclosed is a gate driver for the Si—GaN hybrid switching stage, and a semiconductor power switching stage comprising the gate driver and a Si—GaN hybrid power switching device having a half-bridge or full-bridge switching topology.

A power converter having a slew rate controlling mechanism is provided. A first terminal of a high-side switch is coupled to an input voltage. A first terminal of a low-side switch is connected to a second terminal of the high-side switch. A second terminal of a first capacitor is connected to a node between the second terminal of the high-side switch and the first terminal of the low-side switch. A first terminal of an inductor is connected to the second terminal of the first capacitor and to the node. A first terminal of a second capacitor is connected to a second terminal of the inductor. A second terminal of the second capacitor is grounded. An input terminal of a current controlling device is connected to a power output terminal of a high-side buffer. An output terminal of the current controlling device is connected to the node.

A half bridge GaN circuit is disclosed. The circuit includes a low side circuit, which has a low side switch, a low side switch driver configured to drive the low side switch, a first level shift circuit configured to receive a first level shift signal, and a second level shift circuit configured to generate a second level shift signal. The half bridge GaN circuit also includes a high side circuit, which has a high side switch configured to be selectively conductive according to a voltage level of a received high side switch signal, and a high side switch driver configured to generate the high side switch signal in response to the level shift signals. A transition in the voltage of the high side switch signal causes the high side switch driver to prevent additional transitions of the voltage level of the high side switch signal for a period of time.