Described embodiments include a rectifier circuit comprising a first resistor with first and second resistor terminals, and a second resistor with third and fourth resistor terminals. The first and third resistor terminals are coupled to an auxiliary power terminal. A current source is coupled between the second resistor terminal and a ground terminal. An amplifier has a first amplifier input coupled to the second resistor terminal, and a second amplifier input coupled to the fourth resistor terminal. A first transistor is coupled between the fourth resistor terminal and a damping terminal, and has a first control terminal coupled to the first amplifier output. A gate drive circuit has an input coupled to the damping terminal. A second transistor is coupled between the damping terminal and a bootstrap supply terminal, and has a second control terminal coupled to an output of the gate drive circuit.

A bootstrap circuit supporting fast charging and discharging and a chip. A voltage measurement module (12) and a switch module (11) are arranged, and the voltage measurement module (12) controls an operating state of the switch module (11); during charging, under a specific condition, the switch module (11) is enabled to be in an on state so as to achieve fast charging of a voltage output end; and during discharging, the purpose of fast discharging is achieved by means of a second field effect transistor (MP5) arranged in the bootstrap circuit.

An amplifier system may include a first stage having a plurality of inputs configured to receive a differential pulse-width modulation input signal and generate an intermediate signal based on the differential pulse-width modulation input signal, a quantizer configured to generate a modulated signal based on the intermediate signal, a single-ended class-D output stage configured to generate a single-ended output signal as a function of the differential pulse-width modulation input signal, a feedback network configured to feed back the single-ended output signal to a first input of the plurality of inputs and to feed back a ground voltage to a second input of the plurality of inputs, a plurality of buffers, each particular buffer configured to receive a respective component of the differential pulse-width modulation input signal and generate a respective buffered component, and an input network coupled between the plurality of buffers and the first stage. Each particular buffer of the plurality of buffers may include a buffering subcircuit configured to buffer the respective component of the differential pulse-width modulation input signal associated with the particular buffer in order to generate the respective buffered component and a biasing subcircuit configured to limit a magnitude of the respective component of the differential pulse-width modulation input signal driven to circuitry of the buffering subcircuit for driving the respective buffered component.

A switch activation system including a charge pump, a load monitor, and a switch driver. The charge pump drives a negative voltage node to a predetermined negative voltage level. The load monitor monitors the charge pump and to assert a break done signal after the charge pump begins driving the negative voltage back to the predetermined negative voltage level after being increased. The switch driver turns on a first electronic switch in response to assertion of a corresponding activation signal and assertion of the break done signal. The break done signal is asserted only after electronic switches being turned off are fully turned off to avoid conflict. The charge pump operates at a frequency based on a difference between a voltage level of the negative voltage node and the predetermined negative voltage level to drive the negative voltage node back to its predetermined level within a predetermined period of time.

A switch control circuit includes a power switch, a first protection unit, and a second protection unit. The power switch has a first terminal coupled to a first voltage terminal for receiving a first voltage, a second terminal coupled to a second voltage terminal for receiving a second voltage, and a control terminal receives a control voltage. In a first mode, the control voltage is greater than the first voltage. In a second mode, when a voltage of the second voltage terminal is smaller than a first reference voltage, the first protection unit pulls down the control voltage to reduce a current flowing through the power switch. When the voltage of the second voltage terminal is smaller than the second reference voltage, the second protection unit pulls down the control voltage to a ground voltage.

Devices having one primary transistor, or a plurality of primary transistors in parallel, protect electrical circuits from overcurrent conditions. Optionally, the devices have only two terminals and require no auxiliary power to operate. In those devices, the voltage drop across the device provides the electrical energy to power the device. A third or fourth terminal can appear in further devices, allowing additional overcurrent and overvoltage monitoring opportunities. Autocatalytic voltage conversion allows certain devices to rapidly limit or block nascent overcurrents.

A gate drive circuit that drives a power device by controlling charge and discharge of gate capacitance of the power device includes: a first semiconductor switch that charges the gate capacitance by being brought into conduction according to a first control signal; a second semiconductor switch that discharges the gate capacitance by being brought into conduction according to a second control signal; and a slew rate control circuit that is connected between a gate of the power device and a ground line, and controls a slew rate during discharge. The slew rate control circuit includes a capacitor and a third semiconductor switch connected in series. The third semiconductor switch is brought into conduction according to the second control signal.

A gate driver includes: an input pin for receiving switching control information from a controller; an output pin for driving a control terminal of a power transistor; a power supply pin for receiving power from an external supply; an input side electrically connected to the input pin; an output side electrically connected to the output pin and the power supply pin; and an isolation structure galvanically isolating the input side and the output side from one another. The output side is configured to transfer a fraction of the power received at the power supply pin to the input side over the isolation structure for powering the input side. The input side is configured to convey the switching control information received at the input pin to the output side over the isolation structure. A power electronic system that includes the gate driver is also described.

A bootstrap gate driver charging circuit arranged to drive the gate of an upper switch (Q.sub.U) and a lower switch (Q.sub.L) connected in series to provide an AC output voltage (400) voltage by alternatively turning on and off according to a predetermined duty cycle of alternate upper switch turn-on and lower switch turn-on phases, the bootstrap gate driver charging circuit comprising: an input terminal; an output terminal; an H-bridge inverter with an inverter input and an inverter output; a charging path; and a bootstrap capacitor. The input inverter is electrically connected to the input terminal, the inverter output is electrically connected to a first end of the bootstrap capacitor, the charging path is electrically connected between a second end of the bootstrap capacitor and a gate driver supply voltage; wherein in response to the lower switch being turned ON and providing a path to ground with respect to the supply voltage.

A control circuit includes a detection module configured to detect an operating condition of a semiconductor switching device; a determining module configured to determine a gate allowable voltage of the semiconductor switching device based on the operating condition; and an output module configured to output a control signal to a driving power supply circuit of the semiconductor switching device based on the gate allowable voltage, to control the driving power supply circuit to provide a gate on voltage that is not higher than the gate allowable voltage and that is positively correlated with the gate allowable voltage for the semiconductor switching device. When the operating condition of the semiconductor switching device becomes better, the gate allowable voltage of the semiconductor switching device is increased.