A high resolution analog to digital converter (ADC) with improved bandwidth senses an analog signal (e.g., a load current) to generate a digital signal. The ADC operates based on a load voltage produced based on charging of an element (e.g., a capacitor) by a load current and a digital to analog converter (DAC) output current (e.g., from a N-bit DAC). The ADC generates a digital output signal representative of a difference between the load voltage and a reference voltage. This digital output signal is used directly, or after digital signal processing, to operate an N-bit DAC to generate a DAC output current that tracks the load current. In addition, quantization noise is subtracted from the digital output signal thereby extending the operational bandwidth of the ADC. In certain examples, the operational bandwidth of the ADC extends up to 100s of kHz (e.g., 200-300 kHz), or even higher.

A method for improving a spurious free dynamic range and a signal-to-noise-and-distortion ratio of a capacitor-resistor combined successive approximation register analog-to-digital converter by capacitor re-configuration, the method including: 1) arranging 128 unit capacitors in a positive array and a negative array, respectively, dividing unit capacitors of symmetrical positions of the positive array and the negative array into groups to yield a total of 128 groups of capacitors; 2) acquiring 128 digital codes corresponding to 128 groups of capacitors; 3) sorting the 128 groups of capacitors from maximum to minimum according to the 128 digital codes obtained in 2), and recording the 128 groups of capacitors after sorting as C.sub.1-C.sub.128; and 4) selecting 64 groups of capacitors from C.sub.33 to C.sub.96, and reconfiguring the 64 groups of capacitors in capacitor arrays of the capacitor-resistor analog-to-digital converter.

A semiconductor device includes: a plurality of input circuits each of which receives one of an analog signal and a digital signal, the input circuits being supplied a power supply; a selector that selects one of the input circuits; and an analog-to-digital (AD) converter that performs AD conversion of an analog signal input to the selected input circuit. After the selector selects one of the input circuits, the selector selects another of the input circuits. When the selector selects one of the input circuits and one digital signal of others of the input circuits is changed, the selector does not select another of the input circuits.

A reference time generator including a first clock source including a reference synthesizer and cesium atomic clock configured to produce a cesium reference signal and a cesium QOT metric, a second clock source including a reference synthesizer and rubidium atomic clock configured to produce a rubidium reference signal and a rubidium QOT metric, and a circuit for selecting from the clock sources one reference signal based on the best QOT metric.

A method in a transmitter circuit of generating a signal comprising a first sequence of OFDM symbols, which are to be transmitted within a frequency sub band of a second sequence of OFDM symbols is disclosed. A first cyclic prefix (CP) of the second sequence of OFDM symbols has a first duration, and a second CP of the second sequence of OFDM symbols has a second duration. In order to generate both the first and the second cyclic prefix with an integer number of equidistant samples, a first sampling rate is required. The method comprises generating the signal comprising the first sequence of OFDM symbols at a second sampling rate, lower than the first sampling rate, and adjusting a sampling phase during CPs.

A semiconductor device includes: a plurality of input circuits each of which receives one of an analog signal and a digital signal, the input circuits being supplied a power supply; a selector that selects one of the input circuits; and an analog-to-digital (AD) converter that performs AD conversion of an analog signal input to the selected input circuit. After the selector selects one of the input circuits, the selector selects another of the input circuits. When the selector selects one of the input circuits and one digital signal of others of the input circuits is changed, the selector does not select another of the input circuits.

A sigma-delta modulator arrangement includes a continuous-time sigma-delta modulator with at least one modulator stage, a digital integrator and a given number of switches. The switches are arranged and configured to convert the continuous-time sigma-delta modulator into a first order incremental sigma-delta analog-to-digital converter comprising the digital integrator. At least a first modulator stage of the continuous-time sigma-delta-modulator, which is coupled with an input of the continuous-time sigma-delta modulator, includes at least one tuning element for adjusting an input signal and/or a feedback signal which are supplied to the first modulator stage.

A method for improving a spurious free dynamic range and a signal-to-noise-and-distortion ratio of a capacitor-resistor combined successive approximation register analog-to-digital converter by capacitor re-configuration, the method including: 1) arranging 128 unit capacitors in a positive array and a negative array, respectively, dividing unit capacitors of symmetrical positions of the positive array and the negative array into groups to yield a total of 128 groups of capacitors; 2) acquiring 128 digital codes corresponding to 128 groups of capacitors; 3) sorting the 128 groups of capacitors from maximum to minimum according to the 128 digital codes obtained in 2), and recording the 128 groups of capacitors after sorting as C.sub.1-C.sub.128; and 4) selecting 64 groups of capacitors from C.sub.33 to C.sub.96, and reconfiguring the 64 groups of capacitors in capacitor arrays of the capacitor-resistor analog-to-digital converter.

Provided is programmable circuit for interfacing with a field device. The circuit includes only one analog-to-digital converter (ADC) configured to receive from the field device one from the group including a current signal and a voltage signal. The received one signal has frequency shift keying tones (FSK) superimposed thereon, the ADC being configured to extract information from the received one signal and the FSK tones simultaneously. Also included is only one digital-to-analog converter configured to drive an output signal to the field device, the output signal (i) including one from the group including a current signal and a voltage signal and (ii) being summed with an FSK-modulated signal.

A method in a transmitter circuit (200) of generating a signal comprising a first sequence of OFDM symbols, which are to be transmitted within a frequency sub band of a second sequence of OFDM symbols is disclosed. A first CP of the second sequence of OFDM symbols has a first duration, and a second CP of the second sequence of OFDM symbols has a second duration. In order to generate both the first and the second cyclic prefix with an integer number of equidistant samples, a first sampling rate is required. The method comprises generating (100) the signal comprising the first sequence of OFDM symbols at a second sampling rate, lower than the first sampling rate, and adjusting (110) a sampling phase during CPs.