An apparatus for correcting a mismatch between a first segment and a second segment of a Digital-to-Analog Converter, DAC, is provided. The first segment generates a first contribution to an analog output signal of the DAC based on a first number of bits of a digital input word for the DAC converter, and the second segment generates a second contribution to the analog output signal based on a second number of bits of the digital input word. The apparatus comprises an input configured to receive the digital input word. Further, the apparatus comprises a first processing circuit for the first number of bits comprising a first filter configured to modify the first number of bits in order to generate first modified bits, and a second processing circuit for the second number of bits comprising a second filter configured to modify the second number of bits in order to generate second modified bits. The apparatus additionally comprises an output configured to output a modified digital input word for the DAC. The modified digital input word is based on the first modified bits and the second modified bits.

A semiconductor chip providing on-chip self-testing of an Analog-to-Digital Converter, ADC, implemented in the semiconductor chip is provided. The semiconductor chip comprises the ADC and a Digital-to-Analog Converter, DAC, configured to generate and supply a radio frequency test signal to the ADC via a supply path. The ADC is configured to generate digital output data based on the radio frequency test signal. The semiconductor chip further comprises a reference data generation circuit configured to generate digital reference data. Additionally, the semiconductor chip comprises a comparator circuit configured to compare the digital output data to the digital reference in order to determine error data.

The present invention discloses a DAC method having signal calibration mechanism is provided. Operation states of current sources are controlled to generate an output analog signal by a DAC circuit according to a codeword of an input digital signal. An echo signal is generated by an echo transmission circuit according to the output analog signal. The codeword is mapped to generate an offset signal by a calibration circuit according to a codeword offset mapping table. The offset signal is processed to generate an echo-canceling signal by an echo-canceling circuit. By a calibration parameter calculation circuit, offset amounts are generated according to a difference between the echo signal and the echo-canceling signal, the offset amounts are grouped to perform statistic operation according to the operation states and current offset values are calculated according to calculation among groups and converted to codeword offset values to update the codeword offset mapping table.

Provided are an analog-to-digital (AD) converter, a sensor system, and a test system capable of reducing the time for test processing. AD converter includes input part, AD conversion part, first output part, and second output part. The analog signal output from sensor is input to input part. AD conversion part digitally converts an analog signal to generate first digital data and second digital data. First output part outputs the first digital data to control circuit. Second output part outputs the second digital data to test controller before first output part outputs the first digital data. In the test mode, test controller determines whether or not sensor system including sensor is in an abnormal state on the basis of the second digital data.

An Analog-to-Digital Converter (ADC) includes a plurality of ADC channels connected to an in-service signal input via an isolated power combiner; an on-chip circuit including a calibration source connected to the isolated power combiner; and one or more switches configured to switch the ADC between an in-service mode and a calibration mode. The one or more switches are set such that, in the calibration mode, the in-service signal input is disconnected and the on-chip circuit is connected to the isolated power combiner, and, in the in-service mode, the in-service signal input is connected and the on-chip circuit is disconnected to the isolated power combiner. In the calibration mode, the on-chip circuit is configured to provide a test signal to the plurality of ADC channels for a determination of interleave errors in the plurality of ADC channels.

The present invention discloses a DAC method having signal calibration mechanism is provided. Operation states of current sources are controlled to generate an output analog signal by a DAC circuit according to a codeword of an input digital signal. An echo signal is generated by an echo transmission circuit according to the output analog signal. The codeword is mapped to generate an offset signal by a calibration circuit according to a codeword offset mapping table. The offset signal is processed to generate an echo-canceling signal by an echo-canceling circuit. By a calibration parameter calculation circuit, offset amounts are generated according to a difference between the echo signal and the echo-canceling signal, the offset amounts are grouped to perform statistic operation according to the operation states and current offset values are calculated according to calculation among groups and converted to codeword offset values to update the codeword offset mapping table.

An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit and a controlling circuit. The ADC circuits are configured to generate first quantized outputs according to clock signals. The calibration circuit is configured to perform at least one error operation according to the first quantized outputs to generate second quantized outputs, and is configured to analyze time difference information of the clock signals according to the second quantized outputs to generate adjustment signals. The controlling circuit is configured to analyze the first quantized outputs to generate at least one control signal to the calibration circuit, wherein the at least one control signal is configured to control the calibration circuit to selectively perform the at least one error operation and selectively analyze the time difference information of the clock signals.

An analog-to-digital converter of one embodiment in the present disclosure may comprise a first conversion unit generating an internal clock signal, generating a first digital code and a residual signal by converting an input signal in a successive approximation register (SAR) method in response to the internal clock signal and generating a flash clock signal in response to an external clock signal, a second conversion unit generating a second digital code by converting the residual signal in a flash method in response to the flash clock signal, and an output circuit generating an output digital signal in response to the first digital code and the second digital code.

A system is disclosed herein. The system includes a splitter board. The splitter board includes a microprocessor, a converter, and a bypass relay. The converter includes analog-to-digital circuitry and digital-to-analog circuitry. The bypass relay is configurable between a first state and a second state. In the first state, the bypass relay is configured to direct an input signal to the converter. The converter converts the input signal to a converted input signal and splits the converted input signal into a first portion and a second portion. The first portion is directed to the microprocessor. The second portion is directed to an output port of the splitter board for downstream processes. In the second state, the bypass relay is configured to cause the input signal to bypass the converter. The bypass relay directs the input signal to the output port of the splitter board for the downstream processes.

A system is provided that includes electrodes configured to be implanted in a body, and a pulse generator (PG) circuitry to deliver a stimulus to one or more of the electrodes. The system also includes sensing circuitry configured to define a sensing channel between one or more of the electrodes to sense signals indicative of a physiologic activity of interest, and the sensing circuitry further configured to collect a calibration signal over the sensing channel. The sensing circuitry and PG circuitry are housed within an implantable medical device (IMD). The system also includes one or more processors configured to determine a signal characteristic of interest (COI) of the calibration signal. The one or more processors are also configured to compare a signal COI of the stimulus to the signal COI of the calibration signal, and adjust a parameter of the sensing circuitry or PG circuitry based on the comparison.