An N-bit type charge redistribution analog-to-digital conversion device includes an input terminal configured to receive an input signal and coupled via a line to an output terminal. The output terminal is configured to be coupled to a comparator. The device further includes three reference potential sources of different values and a network of capacitors, where a first terminal of each capacitor is coupled to the line, and where a second terminal of each capacitor is coupled to switching circuit configured for coupling the second terminal of each capacitor to one of the reference potentials.

A transceiver includes a first digital-to-analog converter (DAC) configured to receive a first digital code and output a first current to a first node; a second DAC configured to receive a second digital code and output a second current to a second node; first and second shunt resistors configured to shunt the first node and second nodes to a DC (direct current) node; a first DC coupling resistor coupling the first node to a third node; a second DC coupling resistor coupling the second node to the third node; an AC (alternate current) coupling capacitor coupling the third node to a fourth node; a transimpedance amplifier configured to receive an input current from the fourth node and output an output current to a fifth node; an inductive load configured to shunt the fifth node to a DC node; and an analog-to-digital conversion unit configured to receive a voltage at the fifth node and output a third digital code.

A transceiver includes a first digital-to-analog converter (DAC) configured to receive a first digital code and output a first current to a first node; a second DAC configured to receive a second digital code and output a second current to a second node; first and second shunt resistors configured to shunt the first node and second nodes to a DC (direct current) node; a first DC coupling resistor coupling the first node to a third node; a second DC coupling resistor coupling the second node to the third node; an AC (alternate current) coupling capacitor coupling the third node to a fourth node; a transimpedance amplifier configured to receive an input current from the fourth node and output an output current to a fifth node; an inductive load configured to shunt the fifth node to a DC node; and an analog-to-digital conversion unit configured to receive a voltage at the fifth node and output a third digital code.

A multi-level capacitive digital-to-analog converter, comprises at least one capacitor switch circuit (100) including a differential operational amplifier (130) having a first input node (E130a) and a second input node (E130b). A first current path (101) is coupled to a first reference input terminal (E100a) to apply a first reference potential (RefP) and the second current path (102) is coupled to a second reference input terminal (E100b) to apply a second reference potential (RefN). The at least one capacitor switch circuit (100) comprises a first controllable switch (111) being arranged between the second input node (E130a) of the differential operational amplifier (130) and the first current path (101). The at least one capacitor switch circuit (100) comprises a second controllable switch (112) being arranged between the first input node (E130a) of the differential operational amplifier (130) and the second current path (102).

A digital-to-analog converter (DAC) is described having a digital input, an analogue output, and two capacitors. The DAC has a controller. The controller is configured to generate a switching sequence including at least two switch cycles dependent on the input value received on the digital input. If the input value corresponds to an odd number, in a first switch cycle during a switch cycle first phase, the controller switchably couples a reference voltage to a first terminal and a ground voltage to a second terminal of one of the two capacitors, and switchably couples a ground voltage to a first terminal and the reference voltage to a second terminal of the other of the two capacitors. During a switch cycle second phase, the controller switchably couples a ground voltage to the first terminal and the analogue output to the second terminal of both capacitors.

Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example system for digital-to-analog conversion generally includes a first digital-to-analog converter (DAC) having an input coupled to an input node of the system and a mixing-mode DAC having an input coupled to an input node of the system. The mixing-mode DAC may include a second DAC and a mixer, an output of the second DAC being coupled to an input of the mixer. The system may also include a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the mixer is coupled to a second input of the combiner.

The present application discloses a low-voltage digital to analog conversion circuit, a data driving circuit and a display system. At least one voltage dividing unit comprises a number of resistors connected in series between a lower limit of voltage and an upper limit of voltage, and voltage dividing output terminals drawn from the resistors' connection nodes and an upper limit of voltage connection end. Introducing the voltage dividing unit renders the low-voltage digital signal to analog signal conversion circuit, the data driving circuit, and the display system low-voltage devices with low power consumption and small chip area.

The present application discloses a low-voltage digital to analog conversion circuit, a data driving circuit and a display system. At least one voltage dividing unit comprises a number of resistors connected in series between a lower limit of voltage and an upper limit of voltage, and voltage dividing output terminals drawn from the resistors' connection nodes and an upper limit of voltage connection end. Introducing the voltage dividing unit renders the low-voltage digital signal to analog signal conversion circuit, the data driving circuit, and the display system low-voltage devices with low power consumption and small chip area.

Certain aspects of the present disclosure generally relate to circuitry and techniques for digital-to-analog conversion. One example system for digital-to-analog conversion generally includes a first digital-to-analog converter (DAC) having an input coupled to an input node of the system and a mixing-mode DAC having an input coupled to an input node of the system. The mixing-mode DAC may include a second DAC and a mixer, an output of the second DAC being coupled to an input of the mixer. The system may also include a combiner, wherein an output of the first DAC is coupled to a first input of the combiner, and wherein an output of the mixer is coupled to a second input of the combiner.

To reduce distortion of output analog signals generated at a current-output DA converter. A DA converter that outputs a differential analog signal corresponding to an input digital signal is provided, including: a current output unit outputting a current corresponding to the digital signal to each of first and second wires; a converting unit outputting, as positive-side and negative-side analog signals, voltage signals based on currents flowing through the first and second wires, respectively; a first noise reducing unit having: a first switch switched to be or not to be electrically connected with the first wire; and a first buffer provided between the first switch and a reference potential; and a second noise reducing unit having: a second switch switched to be or not to be electrically connected with the second wire; and a second buffer provided between the second switch and the reference potential.