Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.

In some embodiments, an apparatus comprises a device clock configured to generate a device clock signal a synchronization (SYSREF) clock generation circuit configured to receive the device clock signal from the device clock. The SYSREF clock generating circuit comprises a SYSREF divider configured to generate a SYSREF clock at least partially according to the device clock signal, an interpolator configured to generate a shifted clock at least partially according to the device clock signal, and a latch coupled to the SYSREF divider and the interpolator and configured to sample the SYSREF clock at a rising edge of the shifted clock.

An apparatus includes a transmitter circuit coupled to a termination resistor. The transmitter circuit generates a number of link pulses. A driver circuit is coupled to the transmitter circuit to control a dynamic range of the link pulses. A transformer couples the termination resistor via a transmission medium to a far-end transceiver. The driver circuit controls the dynamic range of the link pulses by providing complementary digital input signals to the transmitter circuit, and the complementary digital input signals include ramp sections.

An apparatus includes a transmitter circuit coupled to a termination resistor. The transmitter circuit generates a number of link pulses. A driver circuit is coupled to the transmitter circuit to control a dynamic range of the link pulses. A transformer couples the termination resistor via a transmission medium to a far-end transceiver. The driver circuit controls the dynamic range of the link pulses by providing complementary digital input signals to the transmitter circuit, and the complementary digital input signals include ramp sections.

One example relates to a monitoring circuit that includes a capacitive digital-to-analog converter that receives a binary code, a reference voltage, a monitored voltage, and a ground reference, the capacitive digital-to-analog converter outputting an analog signal based on the binary code, the reference voltage, the monitored voltage, and the ground reference. The monitoring circuit further includes a comparator including a first input coupled to receive the analog signal and a second input coupled to the reference voltage, the comparator comparing the analog signal to the reference voltage and outputting a comparator signal based on the comparison. The monitoring circuit yet further includes a binary code generator that generates the binary code based on the comparator signal, the binary code approximating a magnitude of the monitored voltage.

One example relates to a monitoring circuit that includes a capacitive digital-to-analog converter that receives a binary code, a reference voltage, a monitored voltage, and a ground reference, the capacitive digital-to-analog converter outputting an analog signal based on the binary code, the reference voltage, the monitored voltage, and the ground reference. The monitoring circuit further includes a comparator including a first input coupled to receive the analog signal and a second input coupled to the reference voltage, the comparator comparing the analog signal to the reference voltage and outputting a comparator signal based on the comparison. The monitoring circuit yet further includes a binary code generator that generates the binary code based on the comparator signal, the binary code approximating a magnitude of the monitored voltage.

A source driver is disclosed, including a data exchanger configured to receive a predetermined number of units of data and store the data corresponding to a predetermined number of channels, and a latch unit configured to store the data output from the data exchanger. The data exchanger mutually exchanges data corresponding to two channels included in each of a plurality of groups, and independently exchanges data for each of the plurality of groups, in which each of the plurality of groups includes two adjacent channels.

A source driver is disclosed, including a data exchanger configured to receive a predetermined number of units of data and store the data corresponding to a predetermined number of channels, and a latch unit configured to store the data output from the data exchanger. The data exchanger mutually exchanges data corresponding to two channels included in each of a plurality of groups, and independently exchanges data for each of the plurality of groups, in which each of the plurality of groups includes two adjacent channels.

System and method for error amplification and processing. For example, the system includes: a signal processing unit configured to receive a reference signal and a feedback signal and generate a digital pulse signal, a frequency of the digital pulse signal being associated with a difference between the reference signal and the feedback signal; a counter configured to receive the digital pulse signal and generate a counter output signal based on at least information associated with the digital pulse signal; and a digital-to-analog converter configured to receive the counter output signal and generate an output signal based on at least information associated with the counter output signal.

System and method for error amplification and processing. For example, the system includes: a signal processing unit configured to receive a reference signal and a feedback signal and generate a digital pulse signal, a frequency of the digital pulse signal being associated with a difference between the reference signal and the feedback signal; a counter configured to receive the digital pulse signal and generate a counter output signal based on at least information associated with the digital pulse signal; and a digital-to-analog converter configured to receive the counter output signal and generate an output signal based on at least information associated with the counter output signal.