System and methods described herein includes a method for iterative decoding. The method includes instantiating an iterative decoding procedure to decode a codeword. At each iteration of the iterative decoding procedure, the method further includes retrieving information relating to a plurality of current decoding variables at a current iteration, determining a first current decoding variable to be skipped for the current iteration based on the information, and processing a second decoding variable without processing the first decoding variable to update related decoding variables from the plurality of current decoding variables.

Methods and systems are disclosed for decoding codewords, wherein codewords comprise at least one circulant and are stored in a first dimension of a matrix, and wherein each circulant in a codeword is associated with a location in a second dimension in the matrix. The method includes determining whether a first location in a second dimension of a first circulant of a first codeword corresponds to a second location in the second dimension of a second circulant of a second codeword. The method includes, in response to determining that the first location does not correspond to the second location, decoding the first and second circulant with a first decoding process. The method includes, in response to determining that the first location corresponds to the second location, decoding the first and second circulant with a second decoding process.

Systems, methods, and devices for encoding and decoding data packets for transmission across a data network. To encode, data packets are first subjected to a an outer code process to result in outer coded packets. The outer coded packets are then divided into generations or groups of outer coded packets, each group or generation having an equal number of packets. Output packets are then created by forming random linear combinations of the outer coded packets from a specific generation or group of outer coded packets. The coefficients for the various elements of each linear combination is selected from a Galois field of values. To decode the incoming packets, enough packets are received until an iterative decoding process can be initiated.

A detection circuit performs a turbo detection process to recover a frame of data symbols from a received signal, the data symbols of the frame having been effected, during transmission, by a Markov process with the effect that the data symbols of the frame in the received signal are dependent one or more preceding data symbols which can be represented as a trellis having a plurality of trellis stages. The detection circuit comprises a plurality of processing elements, each of the processing elements is associated with one of the trellis stages representing the dependency of the data symbols of the frame according to the Markov process and each of the processing elements is configured to receive one or more soft decision values corresponding to one or more data symbols associated with the trellis stage, and each of one or more of the processing elements is configured, in one clock cycle to receive fixed point data representing a priori forward state metrics a priori backward state metrics, and fixed point data representing a priori soft decision values for the one or more data symbols being detected for the trellis stage. For each of a plurality of clock cycles of the turbo detection process, the detection circuit is configured to process, for each of the processing elements representing the trellis stages, the a priori information for the one or more data symbols being detected for the trellis stage associated with the processing element, and to provide the extrinsic soft decision values corresponding to the one or more data symbols for a next clock cycle of the turbo detection process.

It is disclosed an optical coherent receiver comprising a number of decoding blocks configured to implement iterations of a FEC iterative message-passing decoding algorithm. The decoding blocks are distributed into two (or more) parallel chains of cascaded decoding blocks. The receiver also comprises an intermediate circuit interposed between the two parallel chains. The optical coherent receiver is switchable between (i) a first operating mode, in which the intermediate circuit is inactive and the two parallel chains separately implement the FEC message-passing decoding algorithm on respective client channels; and (ii) a second operating mode, in which the intermediate circuit is active and the two parallel chains jointly implement the FEC message-passing decoding algorithm on a same client channel, by cooperating through the intermediate circuit.

A failure resilient distributed replicated data storage system is described herein. The storage system includes zones that are independent, and autonomous from each other. The zones include nodes that are independent and autonomous. The nodes include storage devices. When a data item is stored, it is partitioned into a plurality of data objects and a plurality of parity objects calculated. Reassembly instructions are created for the data item. The data objects and parity objects are spread across all nodes and zones in the storage system. Reassembly instructions are also spread across the zones. When a read request is received, the data item is prepared from the lowest latency nodes according to the reassembly instructions. This provides for data resiliency while keeping the amount of storage space required relatively low.

Systems and method relating generally to solid state memory, and more particularly to systems and methods for recycling data in a solid state memory. The systems and methods include receiving a data set maintained in a memory device, applying at least one iteration of a data decoding algorithm to the data set by a data decoder circuit to yield a decoded output, counting the number of iterations of the data decoding algorithm applied to the data set to yield an iteration count, and recycling the data set to the memory device. The recycling is triggered based at least in part on the iteration count.

Example apparatus and methods provide improved reclamation, garbage collection (GC) and defragmentation (defrag) for data storage devices including solid state drives (SSD) or shingled magnetic recording (SMR) drives. An erasure code (EC) layer that facilitates logically or physically erasing data from the SSD or SMR as a comprehensive GC or defrag is added to the SSD or SMR. Erased data may be selectively recreated from the EC layer as needed. Pre-planned EC write zones may be established to further optimize GC and defrag. Recreated data may be written to selected locations to further optimize SSD and SMR performance. Erasure code data may be distributed to co-operating devices to further improve GC or defrag. Example apparatus and methods may also facilitate writing data to an SMR drive using tape or VTL applications or processes and providing a pseudo virtual tape library on the SMR drive.

A network system for increasing data throughput and decreasing transmission delay from a source node to a sink node via a relay node. The network system may comprise a source node configured to encode a plurality of data packets using rateless coding and transmit the plurality of data packets; at least one relay node configured to receive at least one of the plurality of data packets from the source node, and if the at least one relay node has received a sufficient quantity of the plurality of data packets, regenerate, re-encode, and relay the plurality of data packets; and a sink node configured to receive one or more of the plurality of data packets from the at least one relay node, and if the sink node has received the sufficient quantity of the plurality of data packets, regenerate and decode the plurality of data packets.

An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.