A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2.sup.N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.

Systems and methods for providing input and output ports to connect to channels are provided. Input and output ports are the basic building blocks to create more complex data routing IP blocks. By aggregating these modular ports in different ways, different implementations of crossbar or Network on Chip (NoC) can be implemented, allowing flexible routing structure while maintaining all the benefits of channels such as robustness against delay variation, data compression and simplified timing assumptions.

A computer-implemented method for data synchronization in a P2P ad hoc network includes retrieving network configuration information identifying a plurality of devices forming the P2P ad hoc network. A time offset between a local physical time at a first device and a local physical time of a second device is determined. A change in a data object of a plurality of data objects stored at a key-value store within the first device is detected, each of the data objects including a synchronization indicator. The data object change is communicated to at least the second device based on the synchronization indicator. Upon receiving confirmation from the at least the second device of receipt of the data object change, the network configuration information is updated with a timestamp based on the time offset and indicative of the local physical time at the first device when the data object change was communicated.

Systems and methods are provided for synchronizing a lower-power idle state. The systems and methods perform operations comprising: initializing, by a master physical layer (PHY) controller, a connection over a network with a slave PHY controller; during initialization, synchronizing a low power idle (LPI) timer of the master PHY controller with a LPI timer of the slave PHY controller; establishing an offset between the LPI timer of the master PHY controller and the LPI timer of the slave PHY controller; and after synchronizing the timer of the master PHY controller with the LPI timer of the slave PHY controller, establishing a link between the master PHY controller and the slave PHY controller to enable the master PHY controller and the slave PHY controller to exchange data.

A subscriber of a wired data network, in particular of a local bus system, having internal clock generator for generating a clock generator signal having a clock generator frequency for the subscriber, a receive circuit for receiving a serial receive data stream, a processing circuit for inputting parallel receive data and for outputting parallel transmit data, and a transmit circuit for transmitting a serial transmit data stream. The receive circuit has a serial-to-parallel converter for converting serial receive data of the serial receive data stream into the parallel receive data. The receive circuit has a synchronization unit for synchronizing the internal clock generator to the data clock frequency contained in the serial receive data stream. The synchronization unit is configured for detecting transitions in the received serial receive data stream and for controlling the clock generator frequency of the internal clock generator as a function of the detected transitions.

A communication method, device, and a storage medium to resolve a problem that information about a clock frequency and a clock phase of a service cannot be correctly transmitted to a receiver or correctly recovered because transparent transmission of the information about the clock frequency and the clock phase of the service cannot be implemented. Because a value of k based on a reference data unit is inserted into a second data flow, and the value of k can indicate a quantity of third data units included between a second data unit and the reference data unit in a first data flow, a receive end device can completely recover the first data flow based on the value of k.

An FPGA based system for decoding PAM-3 signals is disclosed, wherein the system comprises a directional coupler for separating 100BASE-T1 and 1000BASE-T1 master and slave signals, DVGAs for amplifying the master and slave signals, ADCs for sampling the amplified signals, and a FPGA module, wherein the FPGA module is configured for decoding the PAM-3 symbols, in real-time, from oversampled ADCs data using fully pipelined Register Transfer Level (RTL) architecture.

Time recovery techniques are described. A method comprises receiving messages from the first device by the second device in the first network domain, the messages to comprise time information to synchronize a first clock for the first device and a second clock for the second device to a network time, determining the second clock is to recover the network time for the second device without new messages from the first device, retrieving a first set of timestamps previously stored for events in the first network domain using the network time from the second clock, retrieving a second set of timestamps previously stored for the events in the first network domain using a redundant time from a third clock, where the third clock is not synchronized with the first and second clocks, and recovering the network time using a regression model and the redundant time from the third clock.

A first timing error of a network device is determined based at least in part on a first received network message from a timing synchronization source. At a first instance, it is determined whether the first timing error exceeds a threshold. In response to a determination at the first instance that the first timing error exceeds the threshold, a clock of the network device is corrected based at least in part on the first received network message. A second timing error of the network device is determined based at least in part on a second received network message from the timing synchronization source. At a second instance, it is determined whether the second timing error exceeds the threshold. In response to a determination at the second instance that the second timing error does not exceed the threshold, the clock of the network device is allowed to function without correction.

Disclosed retimer modules and methods enable equalizer training during link speed negotiation. One illustrative retimer module includes: an analog to digital converter that uses a sampling clock to digitize a receive signal; an equalizer that converts the digitized receive signal into an equalized signal; a decision element that derives a receive symbol stream from the equalized signal; and a clock recovery module that derives the sampling clock based at least in part on an equalization error of the equalized signal, the sampling clock having a frequency with a range including a baud rate of the receive signal at a first supported speed and including a frequency not less than twice the baud rate of the receive signal at a second supported speed.