A node can include a clock; and mapper circuitry configured to determine a timestamp from the clock, and transmit the timestamp to a second node in a Radio over Ethernet (RoE) frame with the timestamp in a control subtype and with an operational code (opcode) that designates the timestamp is in the frame. The node can also include a demapper circuit configured to receive a second timestamp from the second node in a second RoE frame, and provide the second timestamp to a Differential Clock Recovery (DCR) circuit for adjustment of the clock to a second clock at the second node.

A reception apparatus includes a detection unit that detects occurrence of a phase slip in phase estimation values of time-series received symbol data, and determines an inclination of the phase slip, a delay processing unit that generates first received signal data obtained by delaying received signal data obtained from the time-series received symbol data by one symbol time interval, a phase shift unit that generates second received signal data by performing phase shift according to the inclination, only in a period in which one symbol time interval elapses, on only the received signal data of a symbol time at which the occurrence of the phase slip is detected among pieces of the received signal data, and a remainder processing unit that derives a remainder of a difference between the second received signal data and the first received signal data.

The present disclosure includes a time-to-digital converter (TDC) based RF-to-digital (RDC) data converter for time domain signal processing polar receivers. Polar data conversion achieves better SNR tolerance owing to its phase convergence near the origin in a polar coordinate. The proposed RDC consists of a TDC for phase detection and an analog-to-digital converter (ADC) for amplitude conversion. Unlike the conversional data converter, the proposed ADC's sampling position is guided by the detected phase result from the TDC's output. This TDC assisted data-converter architecture reduces the number of bits required for the ADC. In addition, oversampling is no longer needed. With precisely controlled tunable delay cells and gain compensator, this hybrid data convertor is capable to directly convert Quadrature Amplitude Modulation (QAM) waveforms and Amplitude Phase Shift Keying (APSK) waveforms directly from the RF signal without down-conversion. Thus, the proposed RDC architecture achieves lower power consumption and better performance comparing with conventional I/Q receivers.

A calibration method of an equalizer circuit for a memory storage device is disclosed. The calibration method includes: receiving a first signal; adjusting, by the equalizer circuit, the first signal according to a control parameter to output a second signal; generating a first sampling signal according to a first reference signal and the second signal, wherein the first sampling signal reflects data transmitted by the first signal; and generating a second sampling signal according to a second reference signal and the second signal and adjusting the control parameter according to the second sampling signal to calibrate the equalizer circuit, wherein a voltage value of the first reference signal is different from a voltage value of the second reference signal.

Interface devices and systems that include interface devices are disclosed. In some implementations, a device includes a transceiver configured to transmit and receive data, a lane margining controller in communication with the transceiver and configured to control the transceiver to transmit, through a margin command, to an external device, a request for requesting a state of an elastic buffer of the external device, and control the transceiver to receive the state of the elastic buffer of from the external device, and a port setting controller adjust a clock frequency range of a spread spectrum clocking scheme based on the state of the elastic buffer.

A system comprising transmission circuitry to communicate first data to receiver circuitry over a serial communication link during an active state of the serial communication link; and power adjustment circuitry to adjust a power level of the transmission circuitry responsive to a request based on at least one margin measurement performed by the receiver circuitry on the first data, wherein the transmission circuitry is to communicate second data using the adjusted power level over the serial communication link.

A communication device including one or more processors configured to generate a modulated signal, wherein the signal is modulated according to a modulation scheme; send the modulated signal; receive a signal error measurement signal representing a signal error of the modulated signal measured by a receiver of the modulated signal; determine a signal adjustment based on the signal error measurement signal; and adjust the modulation scheme based on the determined signal adjustment, wherein the modulations scheme defines a mapping of a plurality of constellation points to the modulated signal; and wherein the plurality of constellation points are configured according to a quadrature amplitude modulation, wherein the quadrature amplitude modulation comprises four corner constellation points.

There is provided a clock and data recovery circuit for a high-speed PAM-4 receiver through statistical learning. A clock and data recovery device according to an embodiment includes: an input unit through which data is inputted; a clock input unit through which a clock is inputted; a sampling unit configured to sample the inputted data by using the inputted clock; a controller configured to combine results of sampling at a plurality of sampling points, to determine a state of the clock based on the combined results, and to generate a control value for controlling the clock; and an adjustment unit configured to adjust the clock applied to the sampling unit, based on the control value generated by the controller. Accordingly, a hardware structure is simplified and energy efficiency is enhanced compared to an exiting oversampling clock and data recovery circuit for a PAM-4 receiver.

Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.

A transmission device includes a receiver configured to receive a frame signal including synchronization data, main signal data, and an error correction code, a compensator configured to compensate for distortion of the frame signal based on a compensation coefficient, a detector configured to detect synchronization timing of the frame signal from the synchronization data; a corrector configured to correct an error of the frame signal after the distortion is compensated, based on the error correction code according to the synchronization timing, a generator configured to generate a replica signal from the frame signal after the error is corrected by the corrector, based on the synchronization timing, the replica signal corresponding to the frame signal before the distortion is compensated, and an update processor configured to update the compensation coefficient based on the replica signal and the frame signal before the distortion is compensated.