In some aspects, the disclosure is directed to methods and systems for synchronized multi-client content delivery, and a content selection system based on individual and aggregated scores for the content items, to generate bundles or sets of content items having approximately corresponding scores. Server timers and local timers on client devices may be synchronized via notifications, and timer durations dynamically adjusted when client requests and responses are sent prior to client-side timer expiration, but received after server-side timer expiration, indicating communication latency has caused desynchronization. Timers may be adjusted on a global basis or per-client device basis. Through scoring and bundling, sets of content items that may be relevant to approximately an equal share of the recipient client devices may be selected and transmitted.

A method of transition encoding including: receiving a data packet having a packet size; identifying one or more forbidden patterns in the data packet; segmenting the data packet into a plurality of segments based on a location of the one or more forbidden patterns in the data packet; and encoding the plurality of segments by removing the one or more forbidden patterns, and appending position indicator bits according to positions of the segments in the data packet.

Multiphase switched mode power supply clock apparatus, systems, articles of manufacture, and related methods are disclosed. An example apparatus includes a first clock recovery circuit to in response to obtaining a first clock pulse, transmit the first clock pulse to a power converter to cause the power converter to switch based on the first clock pulse, in response to obtaining a second clock pulse after the first clock pulse re-transmit the second clock pulse to a second clock recovery circuit, and increment a count value, and in response to the count value meeting a phase selection value, reset the count value.

In a case where signals branched from a single reference signal source are transmitted via a plurality of cables, a phase synchronization circuit can be used to stabilize a phase of a signal to be outputted from each cable. However, the phases of signal to be outputted from each cable is affected by combination of a length of each cable and an amount of delay caused by feedback control, so that phases of synchronization signals to be outputted from a plurality of transmission paths are not always the same as each other. In the present invention, since a frequency multiplier that multiplies a frequency of a signal outputted from each transmission path by an even number is provided for a phase synchronization circuit, the phases of the synchronization signals to be outputted from the transmission paths are aligned even when signals are branched from one reference signal.

Various example embodiments relate to partial data transmission. A transmitter may receive at least one dataset for transmission. The dataset may be one of a plurality of datasets known to the transmitter and a receiver or to be signaled to the receiver. The transmitter may determine a first portion of the dataset. The size of the first portion may be determined based on a battery level indicator, a latency level associated with the dataset, a radio condition, or a network load. The receiver may recognize the dataset based on the first portion and/or at least one second portion transmitted by the transmitter. Apparatuses, methods, and computer programs are disclosed.

A method applicable to a receiver circuit, including: performing a cross-correlation operation upon at least one time-domain signal on at least one receiver path of the receiver circuit according to a local sequence signal, to estimate at least one time offset amount of the at least one time-domain signal as at least one time offset compensation amount; and, performing time offset compensation upon the at least one time-domain signal on the at least one receiver path according to the at least one time offset compensation amount.

Methods, systems, computer-readable media, and apparatus for spurious information reduction in a data signal are presented. One example of such an apparatus includes an analog-to-digital converter (ADCs) configured to sample a data signal at a plurality of different sampling rates to produce a corresponding plurality of sampled signals; a normalizer configured to obtain a plurality of common-bandwidth signals from at least the plurality of sampled signals; and a common-mode filter configured to produce a digital output signal based on the plurality of common-bandwidth signals.

Included are a demodulation unit 20 that demodulates a received OFDM modulation signal to acquire a demodulated constellation signal, an ideal constellation signal generation unit 312 that generates an ideal constellation signal from the demodulated constellation signal, a data extraction unit 313 that extracts signal data corresponding to subcarriers included in a part of an intermediate frequency section among all frequency sections, from the demodulated constellation signal and the ideal constellation signal, a phase error calculation unit 314 that calculates the phase error of the demodulated constellation signal for the ideal constellation signal, with respect to the extracted signal data, a phase error characteristic estimation unit 315 that estimates the frequency characteristic of the phase error, and a phase error correction unit 316 that corrects the phase error of the demodulated constellation signal, based on the frequency characteristic of the phase error.

A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

Provided are a data signal detection device, and mobile industry processor interface radio frequency front-end device and system. The device includes: a first acquisition circuit, a second acquisition circuit and a selection output circuit. A first input terminal of the first acquisition circuit is connected to a second input terminal of the second acquisition circuit, and a second input terminal of the first acquisition circuit is connected to a first input terminal of the second acquisition circuit. Output terminals of the first acquisition circuit and the second acquisition circuit are connected to two input terminals of the selection output circuit. The acquisition circuit is configured to verify whether an acquisition signal meets a characteristic of a data signal; and the selection output circuit selects an acquisition signal from a received acquisition signal and a received invalid signal for output.