Technologies for managing exact match hash table growth include a network computing device which includes a compute engine and a network interface controller (NIC). The NIC is configured to allocate a plurality of physical bucket addresses in non-contiguous chunks of memory of the compute engine, configure a bucket threshold value as a function of a hash size of the hash table, generate a plurality of virtual bucket addresses as a function of the bucket threshold value, and map each generated virtual bucket address to an allocated physical bucket address. Other embodiments are described herein.

Implementations of this disclosure provide data transmission operations and network interface controllers. An example method performed by a first RDMA network interface controller includes obtaining m data packets from a host memory of a first host; sending the m data packets to a second RDMA network interface controller of a second host; backing up the m data packets to a network interface controller memory integrated into the first RDMA network interface controller; determining that the second RDMA network interface controller does not receive n data packets of the m data packets; and in response, obtaining the n data packets from the m data packets that have been backed up to the network interface controller memory integrated into the first RDMA network interface controller, and retransmitting the n data packets to the second RDMA network interface controller.

An Ethernet adapter module for interfacing a network endpoint device to an Ethernet network is disclosed. The Ethernet adapter module includes an Ethernet medium access controller (MAC) and an Ethernet physical layer device (PHY). The Ethernet MAC includes a processor and Time Sensitive Networking and/or Audio Video Bridging (TSN/AVB) state machines that cooperate with the processor to (1) identify a TSN/AVB request from the network endpoint device, and (2) discover a network topology along which to transfer data between the network endpoint device and a second network endpoint device in accordance with a predetermined Quality of Service (QoS). The Ethernet PHY is coupled to the Ethernet MAC and includes timestamp logic to apply a timing reference to the data being transferred.

A system for processing messages of a high rate data stream and an apparatus including: a message processor including a plurality of processor sub-modules and configured to read an input data stream, process the input data stream, and to output an output data stream; at least one payload memory storing data related to the input data stream and accessible to the message processor; at least one instruction memory accessible to the message processor and storing computer program instructions configuring the message processor to process the input data stream; and an application processor configured to rewrite the at least one instruction memory.

Novel methods of virtualization with unique virtual architectures on field-programmable gate arrays (FPGAs) are provided. A hardware security method can include providing one or more field-programmable gate arrays (FPGAs), and creating an application specialized virtual architecture (or overlay) over the one or more FPGAs (for example, by providing an overlay generator). Unique bitfiles that configure the overlays implemented on the FPGAs can be provided for each deployed FPGA. The application specialized virtual architecture can be constructed using application code, or functions from a domain, to create an overlay represented by one or more hardware description languages (e.g., VHDL).

Technologies for providing streamlined provisioning of accelerated functions in a disaggregated architecture include a compute sled. The compute sled includes a network interface controller and circuitry to determine whether to accelerate a function of a workload executed by the compute sled, and send, to a memory sled and in response to a determination to accelerate the function, a data set on which the function is to operate. The circuitry is also to receive, from the memory sled, a service identifier indicative of a memory location independent handle for data associated with the function, send, to a compute device, a request to schedule acceleration of the function on the data set, receive a notification of completion of the acceleration of the function, and obtain, in response to receipt of the notification and using the service identifier, a resultant data set from the memory sled. The resultant data set was produced by an accelerator device during acceleration of the function on the data set. Other embodiments are also described and claimed.

Implementations of this disclosure provide data transmission operations and network interface controllers. An example method performed by a first RDMA network interface controller includes obtaining m data packets from a host memory of a first host; sending the m data packets to a second RDMA network interface controller of a second host; backing up the m data packets to a network interface controller memory integrated into the first RDMA network interface controller; determining that the second RDMA network interface controller does not receive n data packets of the m data packets; and in response, obtaining the n data packets from the m data packets that have been backed up to the network interface controller memory integrated into the first RDMA network interface controller, and retransmitting the n data packets to the second RDMA network interface controller.

An apparatus and a method for using a signal analyzer are disclosed. The apparatus includes an input port having a first plurality of input channels. The input port generates a digital data stream from each of the first plurality of input channels. The apparatus also includes a trigger bank having a second plurality of trigger processors, each trigger processor receiving a digital data stream chosen from the digital data streams and generating a trigger output having one of a plurality of possible values from the digital data stream. A trigger combiner that receives each of the trigger outputs and generates a trigger signal if the combined trigger outputs satisfy a predetermined criterion. A controller copies the digital data streams to a memory and copies the trigger processor outputs to the memory in response to the trigger combiner generating the trigger signal.

Significantly optimized multi-stage networks, useful in wide target applications, with VLSI layouts using only horizontal and vertical hop wires to route large scale computational blocks having inlet and outlet links, and laid out in an integrated circuit device in a two-dimensional grid arrangement of partial multi-stage hierarchical networks are presented. The optimized multi-stage networks comprising partial multi-stage hierarchical networks employ one or more rings of stages of switches with inlet and outlet links of computational blocks connecting to rings from either left-hand side, or from right-hand side, or from both left-hand side and right-hand side and employ hop wires from outlet links of switches of a first stage of a first ring of a first partial multi-stage hierarchical network are connected to either inlet links of switches of the first or a second stage of the first or a second ring of the first or a second partial multi-stage hierarchical network.

A system for processing messages of a high rate data stream and an apparatus including: a message processor including a plurality of processor sub-modules and configured to read an input data stream, process the input data stream, and to output an output data stream; at least one payload memory storing data related to the input data stream and accessible to the message processor; at least one instruction memory accessible to the message processor and storing computer program instructions configuring the message processor to process the input data stream; and an application processor configured to rewrite the at least one instruction memory.