An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines. Vias to upper and lower metallization line may extend another metallization level.

A circuit board includes a first external circuit layer, a first substrate, a second substrate, a third substrate, and a conductive through hole structure. The first substrate includes conductive pillars electrically connecting the first external circuit layer and the second substrate. The second substrate has an opening and includes a first dielectric layer. The opening penetrates the second substrate, and the first dielectric layer fills the opening. The third substrate includes an insulating layer, a second external circuit layer, and conductive holes. A conductive material layer of the conductive through hole structure covers an inner wall of a through hole and electrically connects the first and the second external circuit layers to define a signal path. The first external circuit layer, the conductive pillars, the second substrate, the conductive holes and the second external circuit layer are electrically connected to define a ground path surrounding the signal path.

A circuit board includes a first substrate, a second substrate, a third substrate, a plurality of conductive structures and a conductive via structure. The second substrate is disposed between the first substrate and the third substrate. The third substrate has an opening and includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The opening penetrates the first dielectric layer and the second dielectric layer, and the third dielectric layer fully fills the opening. The conductive via structure penetrates the first substrate, the second substrate, the third dielectric layer of the third substrate, and is electrically connected to the first substrate and the third substrate to define a signal path. The first substrate, the second substrate, and the third substrate are electrically connected through the conductive structures to define a ground path, and the ground path surrounds the signal path.

Provided is a circuit board, including a first substrate, a second substrate, a third substrate, a fourth substrate, multiple conductive structures, and a conductive via structure. The second substrate is disposed between the first substrate and the third substrate. The third substrate is disposed between the second substrate and the fourth substrate. The third substrate has an opening penetrating the third substrate and includes a first dielectric layer filling the opening. The conductive via structure penetrates the first substrate, the second substrate, the first dielectric layer of the third substrate, and the fourth substrate, and is electrically connected to the first substrate and the fourth substrate to define a signal path. The first substrate, the second substrate, the third substrate and the fourth substrate are electrically connected through the conductive structures to define a ground path, and the ground path surrounds the signal path.

Voids are introduced in a copper shape to reduce warpage experienced by a printed circuit board during a reflow process. Copper shapes on an outer layer of a printed circuit board may be used to connect large packages that include ball grid arrays to the printed circuit board. The copper shapes may induce warpage in the printed circuit board during the reflow process. Routing a mesh pattern of voids in the copper shapes may reduce solder ball joint cracking and pad cratering during reflow and make solder joints more reliable. The voids may make the copper shapes less ridged and change the copper heat dissipation profile to remove sharp warpage forces that cause solder joints to experience pad cratering. The voids may be 8 mil×8 mil cuts or indentations in the copper shape.

Provided are a circuit board, an apparatus and a method for forming a via hole structure. A via hole structure formed on a main body (10) of a circuit board includes a hole (12) enclosed by a conductive layer in the main body (10), the conductive layer constitutes a wall (11) of the hole (12), and a dielectric filling layer (13), which has a dielectric constant smaller than that of the main body (10), is disposed between at least a portion of the wall (11) of the hole (12) and the main body (10), so that the parasitic capacitance of a via hole is decreased, and the impedance of the via hole is increased to become closer to the impedance of a transmission line, thereby effectively improving impedance continuity of a system link.

A substrate structure, a manufacturing method thereof, and an electronic device. The substrate structure includes a substrate, conductive wires and conductive members. Multiple through holes penetrate through the substrate body of the substrate. Multiple first conductive pads are arranged on the first surface of the substrate body. Multiple second conductive pads are arranged on the second surface of the substrate body. The conductive wires are accommodated in the through holes and each has a first end in the first opening of corresponding through hole and a second end in the second opening of corresponding through hole. The conductive members are distributed on the first and second surfaces, and both ends thereof are connected to the corresponding first and second conductive pads through the conductive members. At least part of each conductive wire does not contact the hole wall of each through hole in a direct manner.

An electronic device according to various embodiments of the present invention may comprise a housing; an inner plate which is built into the housing, at least a portion of which is made of a synthetic resin material, and which comprises a first surface, a second surface facing the opposite direction to the first surface, a first through-hole formed in a cone-shaped cross-section the diameter of which gradually decreases the closer to the second surface from the first surface, and a second through-hole formed in a cone-shaped cross-section, which is disposed adjacent to the first through-hole and the diameter of which gradually decreases the closer to the first surface from the second surface; a first conductive line which is formed on the first surface and is formed to overlap with the first through-hole at least partially when viewed from the first surface, a second conductive line which is formed on the second surface and is formed to overlap with the second through-hole at least partially when viewed from the second surface, a first conductive layer which is deposited conformally on an inner wall of the first through-hole and electrically connected to at least one of the first conductive line and the second conductive line, a second conductive layer which is deposited conformally on an inner wall of the second through-hole and electrically connected to at least one of the first conductive line and the first conductive line, and a wireless communication module which is electrically connected to at least one of the first conductive line and the second conductive line, wherein the first conductive line, the second conductive line, the first conductive layer, and the second conductive layer may comprise the same composition of materials. Such an electronic device may vary according to the embodiment.

A printed wiring board includes a first conductor layer, an insulating layer formed on the first conductor layer, a second conductor layer formed on the insulating layer, and a via conductor formed in the insulating layer such that the via conductor is connecting the first and second conductor layers. The insulating layer has opening exposing portion of the first conductor layer such that the via conductor is formed in the opening, the second conductor layer and via conductor are formed such that the second conductor layer and via conductor include a seed layer and an electrolytic plating layer on the seed layer, and the insulating layer includes resin and inorganic particles dispersed in the resin such that the particles include first particles forming inner wall surface in the opening and second particles embedded in the insulating layer and the first particles have shapes different from shapes of the second particles.

A package carrier includes a circuit structure layer and a heat-conducting element. The circuit structure layer includes a notch portion. The heat-conducting element includes a first heat-conducting portion and a second heat-conducting portion vertically connected to the first heat-conducting portion. The notch portion exposes the first heat-conducting portion, and an outer surface of the second heat-conduction portion is aligned with a side surface of the circuit structure layer.