H05K3/22

Embedded-type transparent electrode substrate and method for manufacturing same

A method of manufacturing a transparent electrode substrate according to an exemplary embodiment includes: a) forming a structure including a transparent base, a bonding layer on a surface of the transparent base, and a metal foil on a surface of the bonding layer opposite the transparent base; b) forming a metal foil pattern by patterning the metal foil; c) heat-treating the structure resulting from b) at a temperature of 70° C. to 100° C.; and d) completely curing the bonding layer. Also, a transparent electrode substrate is disclosed.

Substrate structure and the process manufacturing the same

A multi-layer substrate structure to achieve multiple arrangements of power/ground domains is disclosed. The multi-layer substrate structure comprises a first layer for disposing an integrated circuit thereon and a second layer coupled to the first layer, wherein a connection structure is electrically connected to a plurality of power/ground domains on the second layer. With different combinations of the sawing lines and keep-out regions on the multi-layer substrate structure for cutting off some portions of the connection structure, the invention can achieve multiple arrangements of power/ground domains without impacting the customer's PCB or system board design so as to cut short the cycle time for engineering development phase.

Substrate structure and the process manufacturing the same

A multi-layer substrate structure to achieve multiple arrangements of power/ground domains is disclosed. The multi-layer substrate structure comprises a first layer for disposing an integrated circuit thereon and a second layer coupled to the first layer, wherein a connection structure is electrically connected to a plurality of power/ground domains on the second layer. With different combinations of the sawing lines and keep-out regions on the multi-layer substrate structure for cutting off some portions of the connection structure, the invention can achieve multiple arrangements of power/ground domains without impacting the customer's PCB or system board design so as to cut short the cycle time for engineering development phase.

PRINTED CIRCUIT, THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF
20170295639 · 2017-10-12 · ·

A printed circuit, a thin film transistor and manufacturing methods thereof are provided. The printed circuit includes a plurality of metal nanostructures and a metal oxide layer. The metal oxide layer is disposed on a surface of the metal nanostructures and fills a space at an intersection of the metal nanostructures. The metal oxide layer disposed on the surface of the metal nanostructures has a thickness of 0.1 nm to 10 nm.

PRINTED CIRCUIT, THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF
20170295639 · 2017-10-12 · ·

A printed circuit, a thin film transistor and manufacturing methods thereof are provided. The printed circuit includes a plurality of metal nanostructures and a metal oxide layer. The metal oxide layer is disposed on a surface of the metal nanostructures and fills a space at an intersection of the metal nanostructures. The metal oxide layer disposed on the surface of the metal nanostructures has a thickness of 0.1 nm to 10 nm.

MULTI-LEVEL METALIZATION ON A CERAMIC SUBSTRATE
20170290169 · 2017-10-05 ·

A method for producing a copper multi-level metallization on a ceramic substrate consisting of AlN or Al.sub.2O.sub.3. High power regions with metallization having a high current-carrying capacity and low power regions with metallic coatings having a low current-carrying capacity are created on one and the same ceramic substrate. The metallization is printed multiple times in the high power range.

MULTI-LEVEL METALIZATION ON A CERAMIC SUBSTRATE
20170290169 · 2017-10-05 ·

A method for producing a copper multi-level metallization on a ceramic substrate consisting of AlN or Al.sub.2O.sub.3. High power regions with metallization having a high current-carrying capacity and low power regions with metallic coatings having a low current-carrying capacity are created on one and the same ceramic substrate. The metallization is printed multiple times in the high power range.

RESIN SHEET
20170290149 · 2017-10-05 · ·

Resin sheets which includes a support and a resin composition layer in contact on the support, and which are characterized in that an extracted water conductivity A of a cured product of the resin composition layer when extracted at 120° C. for 20 hours is 50 μS/cm or less and an extracted water conductivity B of the cured product of the resin composition layer when extracted at 160° C. for 20 hours is 200 μS/cm or less, can provide a thin insulating layer having excellent insulating properties.

RESIN SHEET
20170290149 · 2017-10-05 · ·

Resin sheets which includes a support and a resin composition layer in contact on the support, and which are characterized in that an extracted water conductivity A of a cured product of the resin composition layer when extracted at 120° C. for 20 hours is 50 μS/cm or less and an extracted water conductivity B of the cured product of the resin composition layer when extracted at 160° C. for 20 hours is 200 μS/cm or less, can provide a thin insulating layer having excellent insulating properties.

PANEL DEVICE AND MANUFACTURING METHOD OF PANEL DEVICE

A panel device including a substrate, a conductor pad, a turning wire, and a circuit board is provided. The substrate has a first surface and a second surface connected to the first surface while a normal direction of the second surface is different from a normal direction of the first surface. The conductor pad is disposed on the first surface of the substrate. The turning wire is disposed on the substrate and extends from the first surface to the second surface. The turning wire includes a wiring layer in contact with the conductor pad and a wire covering layer covering the wiring layer. The circuit board is bonded to and electrically connected to the wire covering layer. A manufacturing method of a panel device is also provided herein.