The present invention discloses a configurable computing array. It is a monolithic integrated circuit comprising at least a configurable computing element and a configurable logic element. The configurable computing element comprises at least a three-dimensional vertical writable memory (3D-W.sub.V) array, which is stacked above the configurable logic element and stores at least a portion of a look-up table (LUT) for a math function.

Provided is a small-area one-time programmable semiconductor memory device that uses a PNPN structure, which is parasitically generated in a CMOS process. An N-type region provided in a location other than both ends or a P-type region provided in a location other than both the ends is put into a floating state so that PNPN current flows, and a thermal breakdown of a resistor caused by this current is used as a memory element.

A pressure sensor and a manufacturing method thereof are provided. The pressure sensor includes a thin-film transistor (TFT) array and a pressure-sensitive layer covering the TFT array. The pressure-sensitive layer includes a plurality of insulating layers and one of one-dimensional materials arranged on the same plane and two-dimensional materials. The insulating layers and the one- or two-dimensional materials are alternately stacked so as to effectively enhance pressure resolution.

The present invention discloses an offset-printing method for a three-dimensional printed memory with multiple bits-per-cell. The mask-patterns for different bits-in-a-cell are merged onto a multi-region data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different bits-in-a-cell.

The present invention discloses an offset-printing method for a three-dimensional 3D-oP (three-dimensional offset-printed memory)-based package. The mask-patterns for different 3D-op dice are merged onto a same data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different 3D-oP dice.

An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.

The present invention discloses an offset-printing method for a three-dimensional printed memory. The mask-patterns for different memory levels are merged onto a multi-region data-mask. At different printing steps, a wafer is offset by different values with respect to the data-mask. Accordingly, data-patterns from a same data-mask are printed into different memory levels.

Provided is a small-area one-time programmable semiconductor memory device that uses a PNPN structure, which is parasitically generated in a CMOS process. An N-type region provided in a location other than both ends or a P-type region provided in a location other than both the ends is put into a floating state so that PNPN current flows, and a thermal breakdown of a resistor caused by this current is used as a memory element.

The present invention discloses a configurable computing array. It is a monolithic integrated circuit comprising at least a configurable computing element and a configurable logic element. The configurable computing element comprises at least a three-dimensional vertical writable memory (3D-W.sub.V) array, which is stacked above the configurable logic element and stores at least a portion of a look-up table (LUT) for a math function.

A memory-array is disclosed in which an array of threshold switching devices is constructed having an area per transistor of 2F.sup.2. This array of threshold switching devices is suitable for a variety of memory or other applications including PRAM, MRAM, RRAM, FRAM, OPT-RAM and 3-D memory.