An integrated circuit device of an embodiment includes a substrate, a first transistor, an insulation layer, a first contact, a second contact, and a first single crystal portion. The first transistor includes a first gate electrode, and a first drain region, and wherein the first source region and the first drain region are disposed in the substrate. The first contact faces the first gate electrode. The second contact faces a first region that is first one of the first source region and the first drain region. The first single crystal portion is disposed on the first region and convex from a surface of the first region, and is located between the first region and the second contact.

Integrated circuits described herein implement an x-input logic gate. The integrated circuit includes a plurality of Schottky diodes that includes x Schottky diodes and a plurality of source-follower transistors that includes x source-follower transistors. Each respective source-follower transistor of the plurality of source-follower transistors includes a respective gate node that is coupled to a respective Schottky diode. A first source-follower transistor of the plurality of source-follower transistors is connected serially to a second source-follower transistor of the plurality of source-follower transistors.

An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.

There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a cell source structure; a first stack structure disposed on the cell source structure; a channel structure penetrating the first stack structure, the channel structure being connected to the cell source structure; and a first peripheral transistor including impurity regions. A level of a bottom surface of each of the impurity regions is higher than that of a bottom surface of the cell source structure, and a level of a top surface of each of the impurity regions is lower than that of a top surface of the cell source structure.

A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

Provided herein may be a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a peripheral circuit structure formed on a substrate including a cell region and a contact region, a cell stacked body formed over the peripheral circuit structure to overlap the cell region, a dummy stacked body formed over the peripheral circuit structure to overlap the contact region, a pillar structure configured to penetrate the cell stacked body, an etch stop layer located over the peripheral circuit structure and overlapping with a bottom surface of the pillar structure, a cutting structure penetrating the pillar structure in a vertical direction and contacting the etch stop layer, and a contact plug penetrating the dummy stacked body and extending to the peripheral circuit structure.

The present application provides a memory device and a manufacturing method of the memory device. The memory device includes a semiconductor substrate defined with an active area over or in the semiconductor substrate and including a recess surrounding the active area; a first dielectric layer disposed over the active area of the semiconductor substrate; a second dielectric layer disposed over the first dielectric layer; and an isolation member disposed within the recess and entirely surrounding the active area.

A semiconductor device includes a semiconductor substrate, a doped region formed in the semiconductor substrate, a source/drain formed in the doped region, a conductive pad formed on the source/drain, a gate dielectric layer disposed over the semiconductor substrate and the doped region exposing the conductive pad, a gate formed on the gate dielectric layer, an insulation layer formed over the gate, the gate dielectric layer, and the conductive pad, and a contact formed in the insulation layer in electric contact with the conductive pad.

Methods of forming a transistor might include removing portions of a semiconductor to define a semiconductor fin having an upper portion having an uppermost surface at a first level and extending from the first level to a second level, and a lower portion, wider than the upper portion, having an uppermost surface at the second level and extending from the second level to a third level; forming first and second isolation regions at the third level and adjacent the lower portion of the semiconductor fin; forming a first dielectric overlying portions of the semiconductor that are lower than a level between the first level and the second level; forming a second dielectric overlying an exposed portion of the upper portion of the semiconductor fin; forming a conductor overlying the second dielectric; and forming first and second source/drains in the lower portion of the semiconductor fin at the second level.

A low cost IC solution is disclosed to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky CMOS all refer to SCMOS. The SCMOS device solutions with a niche circuit element, the complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co/Ti) to P— and N—Si beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros include diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form generic logic gates, memory cores, and analog functional blocks from simple to the complicated, from discrete components to all grades of VLSI chips. Solar photon voltaic electricity conversion and bio-lab-on-a-chip are two newly extended fields of the SCMOS IC applications.