Embodiments of contact structures of a three-dimensional memory device and fabrication method thereof are disclosed. The three-dimensional memory structure includes a film stack disposed on a substrate, wherein the film stack includes a plurality of conductive and dielectric layer pairs, each conductive and dielectric layer pair having a conductive layer and a first dielectric layer. The three-dimensional memory structure also includes a staircase structure formed in the film stack, wherein the staircase structure includes a plurality of steps, each staircase step having two or more conductive and dielectric layer pairs. The three-dimensional memory structure further includes a plurality of coaxial contact structures formed in a first insulating layer over the staircase structure, wherein each coaxial contact structure includes one or more conductive and insulating ring pairs and a conductive core, each conductive and insulating ring pair having a conductive ring and an insulating ring.

A method for manufacturing a semiconductor memory device may include: forming a pre-stack by alternately stacking a plurality of first dielectric layers and a plurality of second dielectric layers over a substrate which has a cell area and a connection area; forming a plurality of slits which pass through the pre-stack, such that a distance between the slits in the connection area is larger than a distance between the slits in the cell area; removing the second dielectric layers in the cell area and in a periphery of the connection area adjacent to the slits while leaving the second dielectric layer in a center of the connection area by injecting an etching solution for removing the second dielectric layers, through the slits; and forming electrode layers in spaces from which the second dielectric layers are removed.

A semiconductor device includes a plurality of first slits disposed at a boundary region of contiguous memory blocks isolating the memory blocks from each other, and disposed to be spaced apart from each other by a predetermined distance in a first direction; at least one word line disposed between the first slits disposed in a square shape; at least one drain selection line disposed over the word line; and a plurality of isolation patterns disposed to isolate each segment of the at least one drain selection line into units of a block. The at least one word line is integrated into a single structure.

Disclosed is a semiconductor device comprising a substrate including a cell array region and a connection region, an electrode structure extending in a first direction on the substrate and including vertically stacked electrodes having pad sections arranged stepwise on the connection region, a first contact plug connected to a first one of the pad sections, a pair of first vertical structures that penetrate the first one of the pad sections and are spaced apart from each other in a first direction by a first distance, a second contact plug connected to a second one of the pad section and having a vertical length that is greater than that of the first contact plug, and a pair of second vertical structures that penetrate the second one of the pad sections and are spaced apart from each other in the first direction by a second distance that is greater than the first distance.

A semiconductor storage device includes a substrate having a memory region and a hook-up region arranged in a first direction and a plurality of memory structures arranged in a second direction intersecting the first direction. The plurality of memory structures include a plurality of conductive layers arranged in a third direction intersecting a surface of the substrate and extending in the first direction over the memory region and the hook-up region and a plurality of contact electrodes provided in the hook-up region and extending in the third direction to have an outer peripheral surface surrounded by a part of the plurality of conductive layers, each contact electrode being connected to any of the plurality of conductive layers. The hook-up region includes a first area and a second area arranged in the first direction. The first region includes a first contact electrode and a second contact electrode, and the second region includes a third contact electrode. A length of the third contact electrode in the third direction is larger than a length of the first contact electrode in the third direction, and is smaller than a length of the second contact electrode in the third direction.

A semiconductor memory device includes a substrate, first conductor layers, second conductor layers, a third conductor layer, and an insulator layer. The substrate includes a first region, a second region, and a third region separating the first and second regions. The first conductor layers are above the first region. The second conductor layers are above an uppermost one of the first conductor layers. The third conductor layer is above the second region. The insulator layer is above the second and third regions. The insulator layer includes first and second portions. The first portion is above the third conductor layer at a height from the substrate greater than a height of the uppermost one of the first conductor layers and extends along a substrate surface direction. The second portion extends along a substrate thickness direction and contacts a surface of the substrate in the third region.

A semiconductor device includes a stacked structure including a first region in which conductive layers and the insulating layers are stacked alternately with each other, and a second region in which sacrificial layers and the insulating layers are stacked alternately with each other, a first slit structure located at a boundary between the first region and the second region and including a first through portion passing through the stacked structure and first protrusions extending from a sidewall of the first through portion, a second slit structure located at the boundary and including a second through portion passing through the stacked structure and second protrusions extending from a sidewall of the second through portion and coupled to the first protrusions, a circuit located under the stacked structure, and a contact plug passing through the second region of the stacked structure and electrically connected to the circuit.

Provided is a memory device including a substrate, a stack structure, a plurality of pads, and a protective layer. The substrate has an array region and a staircase region. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of conductive layers stacked alternately. The pads are disposed on the substrate in the staircase region. The pads are respectively connected to the conductive layers, so as to form a staircase structure. The protective layer is disposed on the stack structure to contact a topmost conductive layer. A top surface of the protective layer adjacent to a topmost pad has a curved profile.

Methods of forming an oxide layer over a semiconductor substrate are provided. The method includes forming a first oxide containing portion of the oxide layer over a semiconductor substrate at a first growth rate by exposing the substrate to a first gas mixture having a first oxygen percentage at a first temperature. A second oxide containing portion is formed over the substrate at a second growth rate by exposing the substrate to a second gas mixture having a second oxygen percentage at a second temperature. A third oxide containing portion is formed over the substrate at a third growth rate by exposing the substrate to a third gas mixture having a third oxygen percentage at a third temperature. The first growth rate is slower than each subsequent growth rate and each growth rate subsequent to the second growth rate is within 50% of each other.

A semiconductor device includes a first structure and a second structure thereon. The first structure includes a substrate, circuit elements on the substrate, a lower interconnection structure electrically connected to the circuit elements, and lower bonding pads, which are electrically connected to the lower interconnection structure. The second structure includes a stack structure including: gate electrodes and interlayer insulating layers, which are alternately stacked and spaced apart in a vertical direction; a plate layer that extends on the stack structure; channel structures within the stack structure, separation regions, which penetrate at least partially through the stack structure, and upper bonding pads, which are electrically connected to the gate electrodes and the channel structures, and are bonded to corresponding ones of the lower bonding pads.