A semiconductor device includes a substrate having a first region and a second region, gate electrodes spaced apart from each other in a first direction, perpendicular to an upper surface of the substrate, and extend in a second direction, and have different lengths on the second region, channel structures that penetrate the gate electrodes, extend in the first direction, and respectively include a channel layer on the first region, support structures that penetrate the gate electrodes and extend in the first direction on the second region, and a separation region that penetrates the gate electrodes and extend in the second direction. The substrate has a recess region that overlaps the separation region in the first direction and extends downward from an upper surface in the second region, adjacent to the first region. The separation region has a protrusion that protrudes downward to correspond to the recess region.

A peripheral circuit structure may be formed on a first surface of a first substrate. A cell array structure may be formed on a first surface of a second substrate and may be attached to the peripheral circuit structure such that those first surfaces face each other. The cell array structure may be formed by forming a back-side via and a preliminary contact pad on the second substrate and forming a semiconductor layer. A hole may be formed to penetrate the semiconductor layer and to expose the preliminary contact pad and may be formed by removing an upper portion of the preliminary contact pad, thereby forming a contact pad separated from the semiconductor layer. The method may further include forming a stack on the semiconductor layer, an insulating layer on the stack, and a contact plug penetrating the insulating layer and connected to the contact pad.

A semiconductor device includes a substrate having cell and connection regions, and a stack structure having dielectric layers and electrodes that are vertically and alternately stacked on the substrate. The stack structure includes a first pad part, a first fence part, a second pad part, and a second fence part that are sequentially arranged along a first direction. Each of the first and second pad parts has a first stepwise structure formed along the first direction and a second stepwise structure formed along a second direction that intersects the first direction, and each of the first and second fence parts includes dummy electrodes at the same levels as the electrodes and spaced apart from the electrodes. Sidewalls of the electrodes that define second stepwise structure of the second part are offset from sidewalls of the dummy electrodes that define second dummy stepwise structure of the first pad part.

Embodiments of semiconductor devices and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure, a second semiconductor structure, and an interposer structure vertically between the first and second semiconductor structures. The first semiconductor structure includes a plurality of logic process-compatible devices and a first bonding layer comprising a plurality of first bonding contacts. The second semiconductor structure includes an array of NAND memory cells and a second bonding layer comprising a plurality of second bonding contacts. The interposer structure includes a first interposer bonding layer having a plurality of first interposer contacts disposed at a first side of the interposer structure, and a second interposer bonding layer having a plurality of second interposer contacts disposed at a second side opposite of the first side of the interposer structure. The first interposer contacts is conductively connected to the second interposer contacts.

An embodiment of a memory device may include a substrate, a first memory array of three-dimensional (3D) NAND cells disposed on the substrate, an isolation trench disposed on the substrate adjacent to the first memory array, and an input/output (IO) contact positioned within the isolation trench. Other embodiments are disclosed and claimed.

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric layer, a vertical stack of discrete silicon nitride memory elements located at levels of the electrically conductive layers, and a vertical stack of discrete silicon oxide blocking dielectric structures laterally surrounding the vertical stack of discrete silicon nitride memory elements. Each of the silicon oxide blocking dielectric structures includes a silicon oxynitride surface region, and an atomic concentration of nitrogen atoms within the silicon oxynitride surface region decreases with a lateral distance from an interface between the silicon oxynitride surface region and a respective one of the silicon nitride memory elements.

A three-dimensional memory device and a manufacturing method thereof. The three-dimensional memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate; and a plurality of through holes passing through the electrode structure in a vertical direction, and including pad regions at the transition between portions of the through holes have different widths.

There are provided a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a gate stack comprising a plurality of first interlayer insulating patterns and a plurality of conductive patterns alternately stacked a dummy stack comprising a plurality of second interlayer insulating patterns and a plurality of sacrificial insulating layers, a plurality of step-shaped grooves defined at different depths in the gate stack, a plurality of openings passing through the dummy stack and spaced apart from each other, a first gap-fill insulating pattern filling the plurality of step-shaped grooves, a second gap-fill insulating pattern filling the plurality of openings, a plurality of conductive gate contacts passing through the first gap-fill insulating pattern and connected to the plurality of conductive patterns, and a plurality of conductive peripheral circuit contacts passing through the second gap-fill insulating pattern.

According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.

A three-dimensional semiconductor memory device includes a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first and second connection regions, and a first block structure on the substrate. The first block structure has a first width on the cell array region, the first block structure has a second width on the first connection region, and the first block structure has a third width on the second connection region. The first, second and third widths are parallel to a second direction intersecting the first direction, and the first width is less than the second width and is greater than the third width.