The present disclosure provides a semiconductor device. The semiconductor device includes a silicide-containing field effect transistor disposed in a periphery region and a floating gate non-volatile memory device disposed in a memory region. The floating gate non-volatile memory device is free of silicide. The floating gate non-volatile memory device includes a second source, a third source, a fourth source, a second drain, and a third drain. The floating gate non-volatile memory device also includes a first floating gate electrode associated with the second source, the second drain, and the third source, and a second floating gate electrode associated with the second source, the third drain, and the fourth source. The second source is disposed between the first and second floating gate electrodes with a constant width. Each of the third source and the fourth source has a width larger than the constant width of the second source.

A memory device includes a first well, a second well, a first active area, a second active area, a third active area, a first poly layer and a second poly layer. The first well is of a first conductivity type. The second well is of a second conductivity type different from the first conductivity type. The first active area is of the second conductivity type and is formed on the first well. The second active area is of the first conductivity type and is formed on the first well and between the first active area and the second well. The third active area is of the first conductivity type and is formed on the second well. The first poly layer is formed above the first well and the second well. The second poly layer is formed above the first well.

A nonvolatile memory device is provided. The device comprises a floating gate having a first finger and a second finger and an active region below the floating gate fingers. A first doped region is in the active region laterally displaced from the first floating gate finger on a first side. A second doped region is in the active region laterally displaced from the first floating gate finger on a second side. A third doped region is in the active region laterally displaced from the second floating gate finger and the second doped region.

A semiconductor device includes a channel region between a source region and a drain region, a gate over the channel region, a dielectric layer over the gate, a capacitive field plate over the dielectric layer, and a word line electrically coupled to the capacitive field plate.

A memory device that provides individual memory cell read, write and erase. In an array of memory cells arranged in rows and columns, each column of memory cells includes a column bit line, a first column control gate line for even row cells and a second column control gate line for odd row cells. Each row of memory cells includes a row source line. In another embodiment, each column of memory cells includes a column bit line and a column source line. Each row of memory cells includes a row control gate line. In yet another embodiment, each column of memory cells includes a column bit line and a column erase gate line. Each row of memory cells includes a row source line, a row control gate line, and a row select gate line.

A semiconductor apparatus with fake functionality includes a logic device and at least one fake device. The logic device is formed on a substrate and turned on by a bias voltage. The fake device is also formed on the substrate. The fake device cannot be turned on by the same bias voltage applied on the logic device.

An erasable programmable non-volatile memory includes a first transistor, a second transistor, an erase gate region and a metal layer. The first transistor includes a select gate, a first doped region and a second doped region. The select gate is connected with a word line. The first doped region is connected with a source line. The second transistor includes the second doped region, a third doped region and a floating gate. The third doped region is connected with a bit line. The erase gate region is connected with an erase line. The floating gate is extended over the erase gate region and located near the erase gate region. The metal layer is disposed over the floating gate and connected with the bit line.

A random number generator device has at least at least a memory unit, a voltage generator, and a control circuit. Each memory unit has two memory cells, one of the two memory cells is coupled to a bias line and a first bit line, and another of the two memory cells is coupled to the bias line and a second bit line. The voltage generator provides the two memory cells a bias voltage, a first bit line voltage and a second bit line voltage via the bias line, the first bit line and the second bit line respectively. The control circuit shorts the first bit line and the second bit line to program the two memory cells simultaneously during a programming period and generates a random number bit according the statuses of the two memory cells during a reading period.

To provide a crystalline oxide semiconductor film, an ion is made to collide with a target including a crystalline In—Ga—Zn oxide, thereby separating a flat-plate-like In—Ga—Zn oxide in which a first layer including a gallium atom, a zinc atom, and an oxygen atom, a second layer including an indium atom and an oxygen atom, and a third layer including a gallium atom, a zinc atom, and an oxygen atom are stacked in this order; and the flat-plate-like In—Ga—Zn oxide is irregularly deposited over a substrate while the crystallinity is maintained.

A memory cell disposed on a substrate has a first gate structure and a second gate structure. The memory cell includes a first heavily doped region adjacent to an outer side of the first gate structure. Further, a first lightly doped drain (LDD) region with a first type dopant is between the first heavily doped region and the outer side of the first gate structure. A pocket doped region with a second type dopant is overlapping with the first LDD region. The second type dopant is opposite to the first type dopant in conductive type. A second heavily doped region is adjacent to an outer side of the second gate structure, opposite to the first heavily doped region. A second LDD region with the first type dopant is disposed between the first gate structure and the second gate structure.