A low-power memory device in which a NAND flash memory and a controller are connected to each other with a short wiring, the controller and a cache memory are connected to each other with a short wiring, and signal transmission delay is small is provided. For example, the NAND flash memory is formed using a Si transistor formed with a single crystal silicon substrate. Since an OS transistor can be formed by a method such as a thin-film method, the cache memory formed using the OS memory can be stacked over the NAND flash memory. When the NAND flash memory and the cache memory are formed in one chip, the NAND flash memory and the controller can be connected to each other with a short wiring, and the controller and the cache memory can be connected to each other with a short wiring.

A semiconductor device with a small variation in transistor characteristics is provided. An oxide semiconductor film, a source electrode and a drain electrode over the oxide semiconductor film, an interlayer insulating film placed to cover the oxide semiconductor film, the source electrode, and the drain electrode, and a gate electrode over the oxide semiconductor film are included; an opening is formed overlapping with a region between the source electrode and the drain electrode in the interlayer insulating film; the gate electrode is placed in the opening in the interlayer insulating film; and the source electrode and the drain electrode include a conductive film having compressive stress.

A manufacturing method of a semiconductor device includes the forming a first oxide over a substrate; depositing a first insulator over the first oxide; forming an opening reaching the first oxide in the first insulator; depositing a first oxide film in contact with the first oxide and the first insulator in the opening; depositing a first insulating film over the first oxide film by a PEALD method; depositing a first conductive film over the first insulating film; and removing part of the first oxide film, part of the first insulating film, and part of the first conductive film until a top surface of the first insulator is exposed to form a second oxide, a second insulator, and a first conductor. The deposition of the first insulating film is performed while the substrate is heated to higher than or equal to 300°.

A semiconductor device with a novel structure is provided. A plurality of memory circuits, a switching circuit, and an arithmetic circuit are included. Each of the plurality of memory circuits has a function of retaining weight data and a function of outputting the weight data to a first wiring. The switching circuit has a function of switching a conduction state between any one of the plurality of first wirings and a second wiring. The arithmetic circuit has a function of performing arithmetic processing using input data and the weight data supplied to the second wiring. The memory circuits are provided in a first layer. The switching circuit and the arithmetic circuit are provided in a second layer. The first layer is provided in a layer different from the second layer.

Since power source voltages are different depending on circuits used for devices, a circuit for outputting at least two or more power sources is additionally prepared. An object is to unify outputs of the power source voltages. A transistor using an oxide semiconductor is provided in such a manner that electrical charge is retained in a node where the transistor and a capacitor are electrically connected to each other, a reset signal is applied to a gate of the transistor to switch the states of the transistor from off to on, and the node is reset when the transistor is on. A circuit configuration that generates and utilizes a potential higher than or equal to a potential of a single power source can be achieved.

A semiconductor device with a small variation in characteristics is provided. The semiconductor device includes a first insulator, a transistor over the first insulator, a second insulator over the transistor, a third insulator over the second insulator, a fourth insulator over the third insulator, and an opening region. The opening region includes the second insulator, the third insulator over the second insulator, and the fourth insulator over the third insulator. The third insulator includes an opening reaching the second insulator. The fourth insulator is in contact with a top surface of the second insulator inside the opening.

A manufacturing method of a semiconductor device includes the forming a first oxide over a substrate; depositing a first insulator over the first oxide; forming an opening reaching the first oxide in the first insulator; depositing a first oxide film in contact with the first oxide and the first insulator in the opening; depositing a first insulating film over the first oxide film by a PEALD method; depositing a first conductive film over the first insulating film; and removing part of the first oxide film, part of the first insulating film, and part of the first conductive film until a top surface of the first insulator is exposed to form a second oxide, a second insulator, and a first conductor. The deposition of the first insulating film is performed while the substrate is heated to higher than or equal to 300°.

A semiconductor device having high on-state current and high reliability is provided. The semiconductor device includes, a first insulator; a first oxide over the first insulator; a second oxide over the first oxide; a first conductor and a second conductor over the second oxide; a third oxide over the second oxide; a second insulator over the third oxide; a third conductor located over the second insulator and overlapping with the third oxide; a third insulator in contact with a top surface of the first insulator, a side surface of the first oxide, a side surface of the second oxide, a side surface of the first conductor, a top surface of the first conductor, a side surface of the second conductor, and a top surface of the second conductor; a fourth insulator over the third insulator; a fifth insulator over the fourth insulator; and a sixth insulator over the third conductor, the second insulator, the third oxide and the fifth insulator. The sixth insulator is in contact with a top surface of each of the third conductor, the second insulator, the third oxide, and the fifth insulator.

A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes a first opening, a second opening, and a third opening which are formed by performing first etching and second etching. By the first etching, the first insulator is etched for forming the first opening, the second opening, and the third opening. By the second etching, the first metal oxide, the second insulator, the third insulator, the fourth insulator, the second metal oxide, and the fifth insulator are etched for forming the first opening; the first metal oxide, the second insulator, and the third insulator are etched for forming the second opening; and the first metal oxide is etched for forming the third opening.

A semiconductor device with a novel structure is provided. The semiconductor device includes a plurality of arithmetic blocks each including an arithmetic circuit portion and a memory circuit portion. The arithmetic circuit portion and the memory circuit portion are electrically connected to each other. The arithmetic circuit portion and the memory circuit portion have an overlap region. The arithmetic circuit portion includes, for example, a Si transistor, and the memory circuit portion includes, for example, an OS transistor. The arithmetic circuit portion has a function of performing product-sum operation. The memory circuit portion has a function of retaining weight data. A first driver circuit has a function of writing the weight data to the memory circuit portion. The weight data is written to all the memory circuit portions included in the same column with the use of the first driver circuit.