A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a transistor including a gate electrode, a source electrode, and a drain electrode; a first insulator over the transistor; a second insulator over the first insulator; a third insulator over the second insulator; a first electrode in contact with the top surface of the source electrode; and a second electrode in contact with the top surface of the drain electrode. The second insulator includes a first opening portion overlapping with the source electrode and a second opening portion overlapping with the drain electrode. The third insulator is in contact with the side surface of the second insulator and the top surface of the first insulator inside the first opening portion and the second opening portion. The first electrode is positioned through the first opening portion. The second electrode is positioned through the second opening portion.

A semiconductor device with improved reliability is provided. The semiconductor device includes a first oxide, a second oxide over the first oxide, a third oxide over the second oxide, and an insulator over the third oxide. The second oxide contains In, an element M (M is Al, Ga, Y, or Sn), and Zn. The first oxide and the third oxide each include a region whose In concentration is lower than that in the second oxide.

A semiconductor device that is suitable for high integration is provided. A first layer provided with a first transistor including an oxide semiconductor, over a substrate; a second layer over the first layer; a third layer provided with a second transistor including an oxide semiconductor, over the second layer; a fourth layer between the first layer and the second layer; and a fifth layer between the second layer and the third layer are included. The total internal stress of the first layer and the total internal stress of the third layer act in a first direction, the total internal stress of the second layer acts in the direction opposite to the first direction, and the fourth layer and the fifth layer each include a film having a barrier property.

A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a first oxide; a first conductor and a second conductor over the first oxide; a first insulator over the first conductor; a second insulator over the second conductor; a second oxide provided over the first oxide and being in contact with the side surface of the first conductor and the side surface of the second conductor; a third oxide provided over the second oxide and including regions in contact with the side surface of the first insulator and the side surface of the second insulator; a third insulator over the third oxide; and a third conductor over the third insulator.

A semiconductor material is an oxide including a metal element and nitrogen, in which the metal element is indium (In), an element M (M is aluminum (Al), gallium (Ga), yttrium (Y), or tin (Sn)), and zinc (Zn) and nitrogen is taken into an oxygen vacancy or bonded to an atom of the metal element.

An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.

A semiconductor device having favorable electrical characteristics is provided. A metal oxide is formed over a substrate by the steps of: introducing a first precursor into a chamber in which the substrate is provided; introducing a first oxidizer after the introduction of the first precursor; introducing a second precursor after the introduction of the first oxidizer; and introducing a second oxidizer after the introduction of the second precursor.

An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. In the memory cell of the array structure, the assist gate region is composed at least two plate capacitors. Especially, the assist gate region at least contains a poly/poly plate capacitor and a metal/poly plate capacitor. The structures and the fabricating processes of the plate capacitors are simple. In addition, the uses of the plate capacitors can effectively reduce the size of the memory cell.

An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. In the memory cell of the array structure, the assist gate region is composed at least two plate capacitors. Especially, the assist gate region at least contains a poly/poly plate capacitor and a metal/poly plate capacitor. The structures and the fabricating processes of the plate capacitors are simple. In addition, the uses of the plate capacitors can effectively reduce the size of the memory cell.

A semiconductor device with a novel structure is provided. One embodiment of the present invention is a semiconductor device including a memory module. The memory module includes a first memory cell, a first wiring, and a second wiring and a third wiring that include a metal oxide. The first memory cell includes a read transistor and a rewrite transistor. The first wiring includes a region functioning as a back gate of the read transistor and a region where the second wiring functions as a conductor. The second wiring includes a region functioning as a channel formation region of the read transistor, a region functioning as a back gate of the rewrite transistor, and a region where the third wiring functions as a conductor. The third wiring includes a region functioning as a channel formation region of the rewrite transistor and a region functioning as a conductor.