A system that includes an energy device having an active region configured to generate or consume electrical energy provided by an electrical current is discussed. A current limiter is disposed between the energy device and a current collector layer. The current limiter controls the current flow between the energy device and the current collector layer. A plurality of electrochemical transistors (ECTs) are arranged in an array such that each ECT in the array provides localized current control for the energy device. Each ECT includes a gate electrode, a drain electrode, a source electrode, and a channel disposed between the drain and the source electrodes. An electrolyte electrically couples the gate electrode to the channel such that an electrical signal at the gate electrode controls electrical conductivity of the channel. The current collector layer is a shared drain or source electrode for the ECTs.

Methods for producing and integrating single-walled carbon nanotubes (SWCNT) into existing TFT backplane manufacturing lines are provided. In contrast to LTPS and oxide TFT backplanes, SWCNT TFT backplanes exhibit either equivalent or better figures of merit such as high field emission mobility, low temperature fabrication, good stability, uniformity, scalability, flexibility, transparency, mechanical deformability, low voltage and low power, bendability and low cost. Methods and processes for integrating SWCNTs technologies into existing TFT backplane manufacturing lines, pilot test and mass production can start without additional capex needs are also provided.

In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure including CNTs embedded in a semiconductor layer is formed, a sacrificial gate structure is formed over the fin structure, the semiconductor layer is doped at a source/drain region of the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, and a source/drain contact layer is formed over the doped source/drain region of the fin structure.

Disclosed are a thin film transistor includes a gate electrode, an active layer including a semiconductor material and a first elastomer, a gate insulator between the gate electrode and the active layer, and a source electrode and a drain electrode electrically connected to the active layer, wherein each of the semiconductor material and the first elastomer has a hydrogen bondable moiety, and the semiconductor material and the first elastomer are subjected to a dynamic intermolecular bonding by a hydrogen bond and a thin film transistor array and an electronic device including the same.

A technique of forming a stack of layers defining electrical circuitry and comprising a plurality of inorganic conductor levels, wherein the method comprises: forming a conductor for at least one of the conductor levels in stages before and after a step of patterning an underlying organic layer.

An integrated circuit (IC) package product, e.g., system-on-chip (SoC) or system-in-package (SiP) product, may include at least one integrated inductor having a core magnetic field (B field) that extends parallel to the substrate major plane of at least one die or chiplet included in or mounted to the product, which may reduce the eddy currents within each die/chiplet substrate, and thereby reduce energy loss of the indictor. The IC package product may include a horizontally-extending IC package substrate, a horizontally-extending die mount base arranged on the IC package substrate, at least one die mounted to the die mount base in a vertical orientation, and an integrated inductor having a B field extending in a vertical direction parallel to the silicon substrate of each vertically-mounted die, thereby providing a reduced substrate loss in the integrated inductor, which provides an increased quality factor (Q) of the inductor.

A technique of producing a device comprising a stack of layers defining an array of transistors and including one or more electrically conductive connections between levels, wherein the method comprises: forming a source-drain conductor pattern defining an array of source conductors each providing an addressing line for a respective set of transistors of the transistor array, and an array of drain conductors each associated with a respective transistor of the transistor array; wherein forming said source-drain conductor pattern comprises: forming a first conductor subpattern which comprises conductor material at least in the regions of the addressing lines and provides the conductive surface of the source-drain conductor pattern at least in the regions where the source and drain conductors are in closest proximity; masking the first conductor subpattern in regions where the source and drain conductors are in closest proximity; thereafter forming a second conductor subpattern, which also comprises conductor material at least in the regions of the addressing lines and which provides the conductive surface of the source-drain conductor pattern in one or more interconnect regions where electrically conductive interlayer connections are to be formed to the source-drain conductor pattern; thereafter de-masking the first conductor subpattern in the regions where the source and drain conductors are in closest proximity; and patterning a layer of semiconductor channel material in situ over the source-drain conductor pattern.

A technique of producing a device comprising a stack of layers defining an array of transistors and including one or more electrically conductive interlayer connections, wherein the method comprises: forming a source-drain conductor pattern defining an array of source conductors each providing an addressing line for a respective set of transistors of the transistor array, and an array of drain conductors each associated with a respective transistor of the transistor array; wherein forming said source-drain conductor pattern comprises forming a first conductor subpattern and thereafter forming a second conductor subpattern, wherein said first conductor subpattern provides the conductive surface of the source-drain conductor pattern in one or more interconnect regions where electrically conductive interlayer connections are to be formed to the source-drain conductor pattern, and the second conductor subpattern provides the conductive surface of the source-drain conductor pattern at least in the regions where the source and drain conductors are in closest proximity.

A conformal organic field-effect transistor includes an elastic substrate, a gate electrode, a polymer insulating layer, an organic semiconductor layer, and a source electrode and a drain electrode from the bottom up, the source electrode and the drain electrode being embedded in the organic semiconductor layer. A method of forming the conformal organic field-effect transistor includes depositing an organic semiconductor on a substrate surface to form an organic semiconductor layer, the source electrode and the drain electrode are embedded in the organic semiconductor layer; then preparing the polymer insulating layer on a surface of the organic semiconductor layer; transferring the gate electrode from the substrate; forming hydroxyl groups on a metal electrode surface of the gate electrode, a polymer insulating layer surface of the source electrode, and a polymer insulating layer surface of the drain electrode, respectively; and then performing alignment and heating to obtain the conformal organic field-effect transistor.

A system that includes an energy device having an active region configured to generate or consume electrical energy provided by an electrical current is discussed. A current limiter is disposed between the energy device and a current collector layer. The current limiter controls the current flow between the energy device and the current collector layer. A plurality of electrochemical transistors (ECTs) are arranged in an array such that each ECT in the array provides localized current control for the energy device. Each ECT includes a gate electrode, a drain electrode, a source electrode, and a channel disposed between the drain and the source electrodes. An electrolyte electrically couples the gate electrode to the channel such that an electrical signal at the gate electrode controls electrical conductivity of the channel. The current collector layer is a shared drain or source electrode for the ECTs.