H10K19/201

Method of fabricating an electrical circuit assembly on a flexible substrate

A method of fabricating an electrical circuit assembly on a flexible substrate comprises: identifying one or more bending-sensitive elements of an electrical circuit assembly, each bending-sensitive element having a performance that varies when said bending-sensitive element is flexed; splitting said one or more bending-sensitive elements into a first portion and a second portion, wherein the first portion and the second portion are functionally equivalent and together equate to said bending-sensitive element; printing the first portion of said bending-sensitive element on a first surface of the flexible substrate; printing the second portion of said bending-sensitive element on a second surface of the flexible substrate, diametrically opposite the first portion such that bending of the flexible substrate has an opposite effect on each of the first and second portions thereby serving to substantially cancel the effect on each portion out; and electrically connecting the first portion and the second portion.

Imaging apparatus and electronic device
10546898 · 2020-01-28 · ·

This technology relates to an imaging apparatus and an electronic device structured to perform pupil correction appropriately. There are provided a photoelectric conversion film configured to absorb light of a predetermined color component to generate signal charges, a first lower electrode configured to be formed under the photoelectric conversion film, a second lower electrode configured to be connected with the first lower electrode, a via configured to connect the first lower electrode with the second lower electrode, and a photodiode configured to be formed under the second lower electrode and to generate signal charges reflecting the amount of incident light. A first distance between the center of the photodiode and the center of the via at the center of the angle of view is different from a second distance therebetween at an edge of the angle of view. The present technology can be applied to imaging apparatuses.

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHOD OF MANUFACTURING THE SAME
20200020717 · 2020-01-16 ·

A three-dimensional (3D) semiconductor memory device may include a stack structure including gate electrodes sequentially stacked on a substrate, and a vertical channel penetrating the stack structure. The gate electrodes may include a ground selection gate electrode, a cell gate electrode, a string selection gate electrode, and an erase gate electrode, which are sequentially stacked on the substrate.

Integrated circuit device and method

An integrated circuit (IC) device includes a substrate and a circuit region over the substrate. The circuit region includes at least one active region extending along a first direction, at least one gate region extending across the at least one active region and along a second direction transverse to the first direction, and at least one first input/output (IO) pattern configured to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction.

Image sensors and methods for manufacturing the same

Image sensors according to some embodiments of the inventive concepts may include a pixel array are including a plurality of pixels, a peripheral area adjacent the pixel array unit, and an organic photoelectric converting layer including a first portion positioned on the pixel area and a second portion positioned on the peripheral area. The second portion may be separated from the first portion.

Three-dimensional semiconductor memory devices

Three-dimensional (3D) semiconductor memory devices are provided. A 3D semiconductor memory device includes an electrode structure on a substrate. The electrode structure includes gate electrodes stacked on the substrate. The gate electrodes include electrode pad regions. The 3D semiconductor memory device includes a dummy vertical structure penetrating one of the electrode pad regions. The dummy vertical structure includes a dummy vertical semiconductor pattern and a contact pattern extending from a portion of the dummy vertical semiconductor pattern toward the substrate.

Semiconductor device and electronic apparatus

A semiconductor device includes a plurality of pixels arranged in a two-dimensional array, each pixel of the plurality of pixels including a photoelectric conversion film configured to photoelectrically convert light of a first wavelength and pass light of a second wavelength, and a photoelectric conversion unit configured to photoelectrically convert the light of the second wavelength. The semiconductor device may further include a charge storage unit configured to store charge received from the photoelectric conversion unit of each pixel in a pixel group, wherein the pixel group includes adjacent pixels among the plurality of pixels, a plurality of through electrodes, and a wiring layer coupled to the photoelectric conversion film of each pixel of the plurality of pixels by at least one through electrode of the plurality of through electrodes. The present technology can be applied to a solid-state imaging element.

Display device and electronic device

A display device with a narrow bezel is provided. The display device includes a pixel circuit and a driver circuit provided on one plane. The driver circuit includes a selection circuit and a buffer circuit. The buffer circuit includes a first transistor and a second transistor. Sources of the first and second transistors are electrically connected with each other. Drains of the first and second transistors are electrically connected with each other. Gates of the first and second transistors are electrically connected with each other. The first transistor and the second transistor are stacked so that the direction of the current flow in the first transistor is parallel to that in the second transistor.

A METHOD OF FABRICATING AN ELECTRICAL CIRCUIT ASSEMBLY ON A FLEXIBLE SUBSTRATE
20190305048 · 2019-10-03 ·

A method of fabricating an electrical circuit assembly on a flexible substrate comprises: identifying one or more bending-sensitive elements of an electrical circuit assembly, each bending-sensitive element having a performance that varies when said bending-sensitive element is flexed; splitting said one or more bending-sensitive elements into a first portion and a second portion, wherein the first portion and the second portion are functionally equivalent and together equate to said bending-sensitive element; printing the first portion of said bending-sensitive element on a first surface of the flexible substrate; printing the second portion of said bending-sensitive element on a second surface of the flexible substrate, diametrically opposite the first portion such that bending of the flexible substrate has an opposite effect on each of the first and second portions thereby serving to substantially cancel the effect on each portion out; and electrically connecting the first portion and the second portion.

BITCELL LAYOUT FOR A TWO-PORT SRAM CELL EMPLOYING VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS
20190279990 · 2019-09-12 ·

Structures for a bitcell of a two-port static random access memory (SRAM) and methods for forming a structure for a bitcell of a two-port SRAM. A storage element of the SRAM includes a first pull-up (PU) vertical-transport field-effect transistor (VTFET) with a fin, a first pull-down (PD) VTFET with a fin that is aligned in a first row with the fin of the first PU VTFET, a second PU VTFET with a fin, and a second PD VTFET with a fin that is aligned in a second row with the fin of the second PU VTFET. The structure further includes a read port coupled with the storage element. The read port includes a read port pull-down (RPD) VTFET with a fin and a read port access (RPG) VTFET with a fin that is aligned in a third row with the fin of the RPG VTFET.