An electronic device may include a first electrode, a first magnetostrictive layer coupled to the first electrode, a plurality of alternating ferromagnetic and insulating layers stacked above the first magnetostrictive layer, a second electrode electrically coupled to an intermediate ferromagnetic layer in the stack of ferromagnetic and insulating layers, a second magnetostrictive layer above the stack of ferromagnetic and insulating layers, and a third electrode electrically coupled to the second magnetostrictive layer. At least one ferromagnetic layer below the intermediate ferromagnetic layer may be switchable between different polarization states responsive to a first voltage applied across the first and second electrodes, and at least one ferromagnetic layer above the intermediate ferromagnetic layer may be switchable between different polarization states responsive to a second voltage applied across the second and third electrodes.

An electronic device may include a first electrode, a first magnetostrictive layer coupled to the first electrode, a plurality of alternating ferromagnetic and insulating layers stacked above the first magnetostrictive layer, a second electrode electrically coupled to an intermediate ferromagnetic layer in the stack of ferromagnetic and insulating layers, a second magnetostrictive layer above the stack of ferromagnetic and insulating layers, and a third electrode electrically coupled to the second magnetostrictive layer. At least one ferromagnetic layer below the intermediate ferromagnetic layer may be switchable between different polarization states responsive to a first voltage applied across the first and second electrodes, and at least one ferromagnetic layer above the intermediate ferromagnetic layer may be switchable between different polarization states responsive to a second voltage applied across the second and third electrodes.

A semiconductor structure includes: a Magnetic Random Access Memory (MRAM) cell, including a bottom electrode, a Magnetic Tunnel Junction (MTJ) stack and a top electrode; an insulating layer covering a sidewall partially and a top surface of the MRAM cell; a first dielectric layer, a stop layer and a second dielectric layer sequentially stacked on the insulating layer; and a top electrode contact hole penetrating through the second dielectric layer, the stop layer, the first dielectric layer and the insulating layer, and extending to the top electrode, where the top electrode contact hole includes a first portion and a second portion connected with each other in the stop layer, and a radial width of the second portion in contact with the top electrode is gradually decreased with an increase in a depth of the top electrode contact hole. Method for manufacturing the structure and semiconductor memory are also provided.

A method of manufacturing a magnetoresistive random-access memory (MRAM) device includes forming an insulating interlayer on a substrate, forming a contact plug extending through the insulating interlayer, forming a first blocking layer covering an upper surface of the contact plug, the first blocking layer including an amorphous material, forming a lower electrode layer on the first blocking layer, and forming a magnetic tunnel junction structure layer on the lower electrode layer.

A laminated seed layer stack with a smooth top surface having a peak to peak roughness of 0.5 nm is formed by sequentially sputter depositing a first seed layer, a first amorphous layer, a second seed layer, and a second amorphous layer where each seed layer may be Mg and has a resputtering rate 2 to 30X that of the amorphous layers that are TaN, SiN, or a CoFeM alloy. A template layer that is NiCr or NiFeCr is formed on the second amorphous layer. As a result, perpendicular magnetic anisotropy in an overlying magnetic layer that is a reference layer, free layer, or dipole layer is substantially maintained during high temperature processing up to 400° C. and is advantageous for magnetic tunnel junctions in embedded MRAMs, spintronic devices, or in read head sensors. The laminated seed layer stack may include a bottommost Ta or TaN buffer layer.

A magnetic tunnel junction element (10) includes a configuration in which a reference layer (14) that includes a ferromagnetic material, a barrier layer (15) that includes O, a recording layer (16) that includes a ferromagnetic material including Co or Fe, a first protective layer (17) that includes O, and a second protective layer (18) that includes at least one of Pt, Ru, Co, Fe, CoB, FeB, or CoFeB are layered.

A magnetic memory device includes a bottom electrode layer, a magnetic tunneling junction (MTJ) stack disposed on the bottom electrode layer, a dielectric cap layer disposed on the MTJ stack, and a metal cap layer disposed on the dielectric cap layer, wherein the metal cap layer comprises a plurality of first metal layers and second metal layers alternately stacked on the dielectric cap layer.

A magnetic memory device includes a bottom electrode layer, a magnetic tunneling junction (MTJ) stack disposed on the bottom electrode layer, a dielectric cap layer disposed on the MTJ stack, and a metal cap layer disposed on the dielectric cap layer, wherein the metal cap layer comprises a plurality of first metal layers and second metal layers alternately stacked on the dielectric cap layer.

Abstract of Disclosure A memory array includes at least one strap region, at least two sub-arrays, a plurality of staggered, dummy magnetic storage elements, and a plurality of bit line structures. The strap region includes a plurality of source line straps and a plurality of word line straps. The two sub-arrays include a plurality of staggered, active magnetic storage elements. The two sub -arrays are separated by the strap region. The staggered, dummy magnetic storage elements are disposed within the strap region. The bit line structures are disposed in the two sub-arrays, and each of the bit line structures is disposed above and directly connected with at least one of the staggered, active magnetic storage elements.

Abstract of Disclosure A memory array includes at least one strap region, at least two sub-arrays, a plurality of staggered, dummy magnetic storage elements, and a plurality of bit line structures. The strap region includes a plurality of source line straps and a plurality of word line straps. The two sub-arrays include a plurality of staggered, active magnetic storage elements. The two sub -arrays are separated by the strap region. The staggered, dummy magnetic storage elements are disposed within the strap region. The bit line structures are disposed in the two sub-arrays, and each of the bit line structures is disposed above and directly connected with at least one of the staggered, active magnetic storage elements.