Patent classifications
H10N52/80
Magnetoresistance effect element and magnetic memory
A magnetoresistance effect element where asymmetry of an inversion current due to a leakage magnetic field from a magnetization fixed layer is decreased. A magnetoresistance effect element includes a first ferromagnetic layer whose magnetization direction is variable, a second ferromagnetic layer whose magnetization direction is fixed, and a nonmagnetic layer sandwiched between the first ferromagnetic layer and the second ferromagnetic layer which are laminated in a first direction which is a lamination direction, where both the first ferromagnetic layer and the second ferromagnetic layer are curved so that central portions of the first and second ferromagnetic layers protrude with respect to outer circumferential portions in the first direction, and protruding directions of the central portions are opposite to each other so that a distance between the outer circumferential portions is larger than a distance between the central portions in the first direction.
SPIN HALL OSCILLATOR
An oscillator includes a spin current source, and a free layer coupled to the spin current source. The free layer has a magnetization hard axis that is parallel to a quantization axis of a spin current injected by the spin Hall effect of the spin current source.
SEMICONDUCTOR DEVICE
A semiconductor device includes a base member, a wiring portion, a semiconductor element, and a resin package. The base member has an obverse surface, a reverse surface, and a side surface connecting the obverse surface and the reverse surface. The semiconductor element is electrically connected to the wiring portion and arranged on the obverse surface of the base member. The resin package covers the semiconductor element. The wiring portion includes an obverse-surface portion formed on the obverse surface, a reverse-surface portion formed on the reverse surface, and a through portion connecting the obverse-surface portion and the reverse-surface portion. The through portion has an exposed surface exposed from the side surface of the base member and a larger portion. The larger portion is positioned more inward than the exposed surface as viewed in the thickness direction of the base member. The larger portion has a dimension larger than the exposed surface in a first direction that is perpendicular to the thickness direction and parallel to the exposed surface.
SPIN-ORBIT TORQUE MAGNETIC RANDOM ACCESS MEMORY
A spin-orbit torque magnetic random access memory includes a substrate, and an SOT memory cell disposed on the substrate and including a magnetic free layer including a ferromagnetic first metal layer, an anti-ferromagnetic second metal layer, and a third metal layer for generating spin-Hall effect. The first metal layer has a thickness ranging from 0.5 nm to 1.5 nm and exhibits perpendicular magnetic anisotropy (PMA). The second metal layer has a thickness greater than 6 nm for providing an exchange bias field. The second metal layer is an IrMn layer not undergone out-of-plane magnetic annealing or coating and exhibiting no PMA. The magnetic free layer has a coercive magnetic field (H.sub.c) upon reaching the critical current density, and |H.sub.EB|>|H.sub.c|.
Semiconductor device with embedded magnetic flux concentrator
A magnetic flux concentrator (MFC) structure comprises a substrate, a first metal layer disposed on or over the substrate, and a second metal layer disposed on or over the first metal layer. Each metal layer comprises (i) a first wire layer comprising first wires conducting electrical signals, and (ii) a first dielectric layer disposed on the first wire layer. A magnetic flux concentrator is disposed at least partially in the first metal layer, in the second metal layer, or in both the first and the second metal layers. The structure can comprise an electronic circuit or a magnetic sensor with sensing plates. The structure can comprise a transformer or an electromagnet with suitable control circuits. The magnetic flux concentrator can comprise a metal stress-reduction layer in the first or second wire layers and a core formed by electroplating the stress-reduction layer.
SPIN TRANSPORT ELECTRONIC DEVICE
An electronic device is presented, the device comprises: a spin accumulating structure; a spin selective filter electrically connected at a first end thereof to a first surface of said spin accumulating layer structure; a charge carrier source attached to said spin selective filter at a second end of the spin selective filter; wherein the spin selective filter is configured to allow passage of the charge carriers having a predetermined spin orientation from the charge carrier source to the spin accumulating structure, thereby causing a variation of spin distribution of the charge carriers within the spin accumulating structure. The device comprises further at least first and second pairs of electrical contacts which are connected to the spin accumulating structure and define first and second electrical paths through said spin accumulating structure, said first and second electrical paths intersecting within said spin accumulating structure. The device including a circuit configured to apply an electrical current between the first pair of electrical contacts and to detect the variation of spin-distribution of charge carriers within the spin accumulating structure by determining electrical voltage between the second pair of electrical contacts in response to the applied electrical current.
Magnetic device and magnetic random access memory
A magnetic memory includes a first spin-orbital-transfer-spin-torque-transfer (SOT-STT) hybrid magnetic device disposed over a substrate, a second SOT-STT hybrid magnetic device disposed over the substrate, and a SOT conductive layer connected to the first and second SOT-STT hybrid magnetic devices. Each of the first and second SOT-STT hybrid magnetic devices includes a first magnetic layer, as a magnetic free layer, a spacer layer disposed under the first magnetic layer, and a second magnetic layer, as a magnetic reference layer, disposed under the spacer layer. The SOT conductive layer is disposed over the first magnetic layer of each of the first and second SOT-STT hybrid magnetic devices.
Magnetic memory and method for controlling the same
A magnetic memory includes a storage element including a first ferromagnetic layer, a first conductive layer which faces the first ferromagnetic layer in a first direction and extends in a second direction different from the first direction, and a first conductive part and a second conductive part which are connected to the first conductive layer at positions which sandwich the first ferromagnetic layer in the second direction when seen in the first direction; and a plurality of first switching elements which are electrically connected to the first conductive part of the storage element.
Magnetic Field Sensor and Method for Making Same
A semiconductor chip for measuring a magnetic field. The semiconductor chip comprises a magnetic sensing element, and an electronic circuit. The magnetic sensing element is mounted on the electronic circuit. The magnetic sensing element is electrically connected with the electronic circuit. The electronic circuit is produced in a first technology and/or first material and the magnetic sensing element is produced in a second technology and/or second material different from the first technology/material.
VOLTAGE-CONTROLLED MAGNETIC-BASED DEVICES HAVING TOPOLOGICAL INSULATOR/MAGNETIC INSULATOR HETEROSTRUCTURE
A voltage-controlled magnetic based device is described that includes a magnetic insulator; a topological insulator adjacent the magnetic insulator; and magnetic dopants within the topological insulator. The magnetic dopants are located within an edge region of the topological insulator to inhibit charge current flow in the topological insulator during a switching operation using an applied electric field generating by applying a switching voltage across two electrodes at opposite sides of the topological insulator. Power dissipation due to carrier-based currents can be avoided or at least minimized by the magnetic dopants at the edges of the topological insulator.