A semiconductor-superconductor hybrid device comprises a semiconductor component and a superconductor component arranged over the semiconductor component. The superconductor component comprises a continuous portion of a superconductor material and a discontinuous portion of a non-ferromagnetic metal. The discontinuous portion is configured to increase the critical field of the superconductor component. It has been found that providing a superconductor component with a discontinuous portion of non-ferromagnetic metal may increase the critical field of the superconductor component, allowing the device to be operated in a stronger magnetic field. Further aspects provide a method of fabricating the device, and the use of a non-ferromagnetic metal to increase the critical field of a superconductor component of a semiconductor-superconductor hybrid device.

A semiconductor-superconductor hybrid device comprises a semiconductor component and a superconductor component arranged over the semiconductor component. The superconductor component comprises a continuous portion of a superconductor material and a discontinuous portion of a non-ferromagnetic metal. The discontinuous portion is configured to increase the critical field of the superconductor component. It has been found that providing a superconductor component with a discontinuous portion of non-ferromagnetic metal may increase the critical field of the superconductor component, allowing the device to be operated in a stronger magnetic field. Further aspects provide a method of fabricating the device, and the use of a non-ferromagnetic metal to increase the critical field of a superconductor component of a semiconductor-superconductor hybrid device.

This disclosure teaches methods for making high-temperature superconducting striated tape combinations and the product high-temperature superconducting striated tape combinations. This disclosure describes an efficient and scalable method for aligning and bonding two superimposed high-temperature superconducting (HTS) filamentary tapes to form a single integrated tape structure. This invention aligns a bottom and top HTS tape with a thin intervening insulator layer with microscopic precision, and electrically connects the two sets of tape filaments with each other. The insulating layer also reinforces adhesion of the top and bottom tapes, mitigating mechanical stress at the electrical connections. The ability of this method to precisely align separate tapes to form a single tape structure makes it compatible with a reel-to-reel production process.

A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.

A method for processing a semiconductor device with two closely space gates comprises forming a template structure, wherein the template structure includes at least one sub-structure having a dimension less than the CD. The method further comprises forming a gate layer on and around the template structure. Then, the method comprises removing the part of the gate layer formed on the template structure, and patterning the remaining gate layer into a gate structure including the two gates. Further, the method comprises selectively removing the template structure, wherein the spacing between the two gates is formed by the removed sub-structure.

A solid state cooler device is disclosed that comprises a first normal metal pad, a first aluminum layer and a second aluminum layer disposed on the first normal metal pad and separated from one another by a gap, a first aluminum oxide layer formed on the first aluminum layer, and a second aluminum oxide layer formed on the second aluminum layer, and a first superconductor pad disposed on the first aluminum oxide layer and a second superconductor pad disposed on the second aluminum oxide layer. The device further comprises a first conductive pad coupled to the first superconductor pad, and a second conductive pad coupled to the second superconductor pad, wherein hot electrons are removed from the first normal metal pad when a bias voltage is applied between the first conductive pad and the second conductive pad.

A method for manufacturing a nanowire includes providing a sacrificial substrate, providing a patterned mask layer on the sacrificial substrate, providing a nanowire on the sacrificial substrate through an opening in the patterned mask layer, and removing the sacrificial substrate. Because the sacrificial substrate is used for growing the nanowire and later removed, the material of the sacrificial substrate can be chosen to be lattice matched with the material of the nanowire without regard to the electrical properties thereof. Accordingly, a high-quality nanowire can be grown and operated without the degradation in performance normally experienced when using a lattice matched substrate.

Devices, systems, methods, computer-implemented methods, apparatus, and/or computer program products that can facilitate an epitaxial Josephson junction transmon device are provided. According to an embodiment, a device can comprise a substrate. The device can further comprise an epitaxial Josephson junction transmon device coupled to the substrate. According to an embodiment, a device can comprise an epitaxial Josephson junction transmon device coupled to a substrate. The device can further comprise a tuning gate coupled to the substrate and formed across the epitaxial Josephson junction transmon device. According to an embodiment, a device can comprise a first superconducting region and a second superconducting region formed on a substrate. The device can further comprise an epitaxial Josephson junction tunneling channel coupled to the first superconducting region and the second superconducting region.

A method of making a film comprising depositing magnesium and boron on a substrate; depositing a capping layer to form a capped film; and cooling the capped film so as to form a magnesium diboride film. The depositing may comprise tuning a ratio of the Mg to the B so as to tailor a resistivity of the magnesium diboride film anywhere in the range 10 μΩ*cm≤ρ≤500 mΩ*cm, and so as to form the magnesium diboride film comprising a superconductive film having a critical temperature greater than 10K or in a range 10K-40K. The magnesium diboride film can have an area greater than or equal to a circular area having a diameter of at least 4 inches; a thickness and sheet resistance varying by less than 10% over an entirety of the area; and a surface roughness less than 2 nm over the entirety of the area.

Techniques and methods to form smooth metal layers deposited onto selected surfaces of Josephson junction devices are provided. For example, one or more embodiments described herein can comprise depositing a layer of a first material comprising metal atom species on a selected surface of a device layer; depositing a layer of a second material on a surface of the layer of first material; and performing plasma etching on the layer of second material and the layer of first material to form an etched surface of the layer of first material that is smoother than the surface of the layer of first material, as deposited.