An electric circuit includes one or more photon detector components and a superconducting logic gate component coupled to respective outputs of the one or more photon detector components. The electric circuit further includes a bias source electrically coupled to the superconducting logic gate component, the bias source configured to provide a bias current adapted to cause the superconducting logic gate component to function as a logical gate. The electric circuit also includes an optical switch component electrically coupled to an output of the superconducting logic gate component.

A circuit includes a resonant circuit and a detection circuit. The detection circuit includes a superconducting component coupled with the resonant circuit, and an impedance component coupled to the superconducting component. The superconducting component is configured to receive an input current. The superconducting component is configured to carry a first current that has a current density that is less than a threshold current density, while the first resonant circuit is in the first state, and carry a second current that has a current density that exceeds the threshold current density while the first resonant circuit is in the second state, thereby transitioning the superconducting component to a non-superconducting state while the resonant circuit is in the second state. A method of operating the detection circuit is also described herein.

A controllable superconducting inductor circuit comprises: a plurality of sub-circuits, each sub-circuit comprising: an inductor element; and a control element coupled to the inductor element to induce current in the inductor element in response to a control signal received at the control element. The inductor elements from the plurality of sub-circuits are arranged in parallel between a first pair of nodes to provide a tunable total inductance L.sub.tun. For each of the plurality of sub-circuits, the inductor element behaves as a superconducting kinetic inductance element when the current induced therein is less than a threshold level and behaves as a normal, non-superconducting inductor when the current induced therein is greater than the threshold level.

Provided are a method and apparatus for calculating fault resistance and a current-limiting current of a superconducting fault current limiter. The method includes: calculating a first short-circuit fault current I.sub.n(t) of a power grid short-circuit fault transient circuit; calling an external characteristic model U(I,t), and calculating resistance R.sub.n(t) of a superconducting fault current limiter under the first short-circuit fault current I.sub.n(t); adding the resistance R.sub.n(t) of the superconducting fault current limiter into the power grid short-circuit fault transient circuit, and calculating a second short-circuit fault current I.sub.m(t), where m=n+1; and determining whether an error between the second short-circuit fault current I.sub.m(t) and the first short-circuit fault current I.sub.n(t) is smaller than a preset threshold value, if yes, determining the fault resistance and the current-limiting current of the superconducting fault current limiter to be R.sub.n(t) and I.sub.m(t) respectively; otherwise, I.sub.n(t)=I.sub.m(t), returning for iteration.

A high temperature superconducting, HTS, field coil. The HTS field coil has a plurality of turns and a semiconductor, arranged such that current can be shared between the turns via the semiconductor.

An electric circuit includes a plurality of superconducting components, each of the plurality of superconducting components having: a respective first terminal; a respective second terminal; and a respective input. The electric circuit further includes a bias current source electrically-connected to the respective first terminal of each of the plurality of superconducting components. The bias current source is configured to provide a bias current adapted to cause the electric circuit to function as a logical OR gate on the respective inputs of the plurality of superconducting components. The electric circuit further includes an output node adapted to output a state of the logical OR gate.

A programmable circuit includes a superconducting component arranged in a multi-dimensional array of alternating narrow and wide portions. The programmable circuit further includes a plurality of heat sources, each heat source configured to selectively provide heat to a respective narrow portion sufficient to transition the respective narrow portion from a superconducting state to a non-superconducting state. The programmable circuit further includes a plurality of electrical terminals, each electrical terminal coupled to a respective wide portion of the multi-dimensional array.

The invention describes a memory device which combines a switchable resistive element and a superconductor element electrically in parallel. The switchable resistive element comprises an active material, which is switchable between first and second values of electrical resistivity ρ.sub.1 and ρ.sub.2 at the same temperature, wherein ρ.sub.1 is different to ρ.sub.2. The superconductor element is operable so that at least part of the superconductor element is switchable from a superconducting state to a non-superconducting state. When the superconductor element is switched from the superconducting state to the non-superconducting state, a current injection is provided through the switchable resistive element capable of switching the switchable resistive element between said first and second values of electrical resistivity.

An electronic component having an asymmetric impedance is provided. The component includes first, second and third branches that connect at a common node. The component includes a first portion of superconducting material disposed along the first branch and a second portion of superconducting material disposed along the second branch. The component includes a first device disposed along the first branch and configured to transition the second portion of the superconducting material to a non-superconducting state when a current between a first terminal of the first device and a second terminal of the first device exceeds a first threshold value and a second device disposed along the second branch and configured to transition the first portion of the superconducting material to a non-superconducting state when a current between a first terminal of the second device and a second terminal of the second device exceeds a second threshold value.

An electronic component having an asymmetric impedance is provided. The component includes first, second and third branches that connect at a common node. The component includes a first portion of superconducting material disposed along the first branch and a second portion of superconducting material disposed along the second branch. The component includes a first device disposed along the first branch and configured to transition the second portion of the superconducting material to a non-superconducting state when a current between a first terminal of the first device and a second terminal of the first device exceeds a first threshold value and a second device disposed along the second branch and configured to transition the first portion of the superconducting material to a non-superconducting state when a current between a first terminal of the second device and a second terminal of the second device exceeds a second threshold value.